2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/delay.h>
17 #include <linux/init.h>
18 #include <linux/smp.h>
21 #include <linux/of_address.h>
22 #include <linux/regmap.h>
23 #include <linux/mfd/syscon.h>
25 #include <linux/reset.h>
26 #include <linux/cpu.h>
27 #include <asm/cacheflush.h>
29 #include <asm/smp_scu.h>
30 #include <asm/smp_plat.h>
31 #include <asm/mach/map.h>
35 static void __iomem *scu_base_addr;
36 static void __iomem *sram_base_addr;
39 #define PMU_PWRDN_CON 0x08
40 #define PMU_PWRDN_ST 0x0c
42 #define PMU_PWRDN_SCU 4
44 static struct regmap *pmu;
46 static int pmu_power_domain_is_on(int pd)
51 ret = regmap_read(pmu, PMU_PWRDN_ST, &val);
55 return !(val & BIT(pd));
58 static struct reset_control *rockchip_get_core_reset(int cpu)
60 struct device *dev = get_cpu_device(cpu);
61 struct device_node *np;
63 /* The cpu device is only available after the initial core bringup */
67 np = of_get_cpu_node(cpu, 0);
69 return of_reset_control_get(np, NULL);
72 static int pmu_set_power_domain(int pd, bool on)
74 u32 val = (on) ? 0 : BIT(pd);
78 * We need to soft reset the cpu when we turn off the cpu power domain,
79 * or else the active processors might be stalled when the individual
80 * processor is powered down.
82 if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
83 struct reset_control *rstc = rockchip_get_core_reset(pd);
86 pr_err("%s: could not get reset control for core %d\n",
92 reset_control_deassert(rstc);
94 reset_control_assert(rstc);
96 reset_control_put(rstc);
99 ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);
101 pr_err("%s: could not update power domain\n", __func__);
107 ret = pmu_power_domain_is_on(pd);
109 pr_err("%s: could not read power domain state\n",
119 * Handling of CPU cores
122 static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
123 struct task_struct *idle)
127 if (!sram_base_addr || !pmu) {
128 pr_err("%s: sram or pmu missing for cpu boot\n", __func__);
133 pr_err("%s: cpu %d outside maximum number of cpus %d\n",
134 __func__, cpu, ncores);
139 ret = pmu_set_power_domain(0 + cpu, true);
143 if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
144 /* We communicate with the bootrom to active the cpus other
145 * than cpu0, after a blob of initialize code, they will
146 * stay at wfe state, once they are actived, they will check
148 * sram_base_addr + 4: 0xdeadbeaf
149 * sram_base_addr + 8: start address for pc
152 writel(virt_to_phys(secondary_startup), sram_base_addr + 8);
153 writel(0xDEADBEAF, sram_base_addr + 4);
161 * rockchip_smp_prepare_sram - populate necessary sram block
162 * Starting cores execute the code residing at the start of the on-chip sram
163 * after power-on. Therefore make sure, this sram region is reserved and
164 * big enough. After this check, copy the trampoline code that directs the
165 * core to the real startup code in ram into the sram-region.
166 * @node: mmio-sram device node
168 static int __init rockchip_smp_prepare_sram(struct device_node *node)
170 unsigned int trampoline_sz = &rockchip_secondary_trampoline_end -
171 &rockchip_secondary_trampoline;
176 ret = of_address_to_resource(node, 0, &res);
178 pr_err("%s: could not get address for node %s\n",
179 __func__, node->full_name);
183 rsize = resource_size(&res);
184 if (rsize < trampoline_sz) {
185 pr_err("%s: reserved block with size 0x%x is to small for trampoline size 0x%x\n",
186 __func__, rsize, trampoline_sz);
190 /* set the boot function for the sram code */
191 rockchip_boot_fn = virt_to_phys(secondary_startup);
193 /* copy the trampoline to sram, that runs during startup of the core */
194 memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz);
196 outer_clean_range(0, trampoline_sz);
203 static const struct regmap_config rockchip_pmu_regmap_config = {
209 static int __init rockchip_smp_prepare_pmu(void)
211 struct device_node *node;
212 void __iomem *pmu_base;
215 * This function is only called via smp_ops->smp_prepare_cpu().
216 * That only happens if a "/cpus" device tree node exists
217 * and has an "enable-method" property that selects the SMP
218 * operations defined herein.
220 node = of_find_node_by_path("/cpus");
222 pmu = syscon_regmap_lookup_by_phandle(node, "rockchip,pmu");
227 pmu = syscon_regmap_lookup_by_compatible("rockchip,rk3066-pmu");
231 /* fallback, create our own regmap for the pmu area */
233 node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-pmu");
235 pr_err("%s: could not find pmu dt node\n", __func__);
239 pmu_base = of_iomap(node, 0);
241 pr_err("%s: could not map pmu registers\n", __func__);
245 pmu = regmap_init_mmio(NULL, pmu_base, &rockchip_pmu_regmap_config);
247 int ret = PTR_ERR(pmu);
251 pr_err("%s: regmap init failed\n", __func__);
258 static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
260 struct device_node *node;
263 node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-smp-sram");
265 pr_err("%s: could not find sram dt node\n", __func__);
269 sram_base_addr = of_iomap(node, 0);
270 if (!sram_base_addr) {
271 pr_err("%s: could not map sram registers\n", __func__);
275 if (rockchip_smp_prepare_pmu())
278 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
279 if (rockchip_smp_prepare_sram(node))
282 /* enable the SCU power domain */
283 pmu_set_power_domain(PMU_PWRDN_SCU, true);
285 node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
287 pr_err("%s: missing scu\n", __func__);
291 scu_base_addr = of_iomap(node, 0);
292 if (!scu_base_addr) {
293 pr_err("%s: could not map scu registers\n", __func__);
298 * While the number of cpus is gathered from dt, also get the
299 * number of cores from the scu to verify this value when
302 ncores = scu_get_core_count(scu_base_addr);
303 pr_err("%s: ncores %d\n", __func__, ncores);
305 scu_enable(scu_base_addr);
309 asm ("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
310 ncores = ((l2ctlr >> 24) & 0x3) + 1;
313 /* Make sure that all cores except the first are really off */
314 for (i = 1; i < ncores; i++)
315 pmu_set_power_domain(0 + i, false);
318 #ifdef CONFIG_HOTPLUG_CPU
319 static int rockchip_cpu_kill(unsigned int cpu)
321 pmu_set_power_domain(0 + cpu, false);
325 static void rockchip_cpu_die(unsigned int cpu)
327 v7_exit_coherency_flush(louis);
333 static struct smp_operations rockchip_smp_ops __initdata = {
334 .smp_prepare_cpus = rockchip_smp_prepare_cpus,
335 .smp_boot_secondary = rockchip_boot_secondary,
336 #ifdef CONFIG_HOTPLUG_CPU
337 .cpu_kill = rockchip_cpu_kill,
338 .cpu_die = rockchip_cpu_die,
341 CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops);