2 * arch/arm/mach-orion5x/wnr854t-setup.c
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
8 #include <linux/gpio.h>
9 #include <linux/kernel.h>
10 #include <linux/init.h>
11 #include <linux/platform_device.h>
12 #include <linux/pci.h>
13 #include <linux/irq.h>
14 #include <linux/delay.h>
15 #include <linux/mtd/physmap.h>
16 #include <linux/mv643xx_eth.h>
17 #include <linux/ethtool.h>
19 #include <asm/mach-types.h>
20 #include <asm/mach/arch.h>
21 #include <asm/mach/pci.h>
22 #include <mach/orion5x.h>
26 static unsigned int wnr854t_mpp_modes[] __initdata = {
27 MPP0_GPIO, /* Power LED green (0=on) */
28 MPP1_GPIO, /* Reset Button (0=off) */
29 MPP2_GPIO, /* Power LED blink (0=off) */
30 MPP3_GPIO, /* WAN Status LED amber (0=off) */
31 MPP4_GPIO, /* PCI int */
35 MPP8_UNUSED, /* ??? */
36 MPP9_GIGE, /* GE_RXERR */
37 MPP10_UNUSED, /* ??? */
38 MPP11_UNUSED, /* ??? */
39 MPP12_GIGE, /* GE_TXD[4] */
40 MPP13_GIGE, /* GE_TXD[5] */
41 MPP14_GIGE, /* GE_TXD[6] */
42 MPP15_GIGE, /* GE_TXD[7] */
43 MPP16_GIGE, /* GE_RXD[4] */
44 MPP17_GIGE, /* GE_RXD[5] */
45 MPP18_GIGE, /* GE_RXD[6] */
46 MPP19_GIGE, /* GE_RXD[7] */
51 * 8M NOR flash Device bus boot chip select
53 #define WNR854T_NOR_BOOT_BASE 0xf4000000
54 #define WNR854T_NOR_BOOT_SIZE SZ_8M
56 static struct mtd_partition wnr854t_nor_flash_partitions[] = {
72 static struct physmap_flash_data wnr854t_nor_flash_data = {
74 .parts = wnr854t_nor_flash_partitions,
75 .nr_parts = ARRAY_SIZE(wnr854t_nor_flash_partitions),
78 static struct resource wnr854t_nor_flash_resource = {
79 .flags = IORESOURCE_MEM,
80 .start = WNR854T_NOR_BOOT_BASE,
81 .end = WNR854T_NOR_BOOT_BASE + WNR854T_NOR_BOOT_SIZE - 1,
84 static struct platform_device wnr854t_nor_flash = {
85 .name = "physmap-flash",
88 .platform_data = &wnr854t_nor_flash_data,
91 .resource = &wnr854t_nor_flash_resource,
94 static struct mv643xx_eth_platform_data wnr854t_eth_data = {
95 .phy_addr = MV643XX_ETH_PHY_NONE,
97 .duplex = DUPLEX_FULL,
100 static struct dsa_chip_data wnr854t_switch_chip_data = {
101 .port_names[0] = "lan3",
102 .port_names[1] = "lan4",
103 .port_names[2] = "wan",
104 .port_names[3] = "cpu",
105 .port_names[5] = "lan1",
106 .port_names[7] = "lan2",
109 static struct dsa_platform_data wnr854t_switch_plat_data = {
111 .chip = &wnr854t_switch_chip_data,
114 static void __init wnr854t_init(void)
117 * Setup basic Orion functions. Need to be called early.
121 orion5x_mpp_conf(wnr854t_mpp_modes);
124 * Configure peripherals.
126 orion5x_eth_init(&wnr854t_eth_data);
127 orion5x_eth_switch_init(&wnr854t_switch_plat_data, NO_IRQ);
128 orion5x_uart0_init();
130 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
131 ORION_MBUS_DEVBUS_BOOT_ATTR,
132 WNR854T_NOR_BOOT_BASE,
133 WNR854T_NOR_BOOT_SIZE);
134 platform_device_register(&wnr854t_nor_flash);
137 static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot,
143 * Check for devices with hard-wired IRQs.
145 irq = orion5x_pci_map_irq(dev, slot, pin);
153 return gpio_to_irq(4);
158 static struct hw_pci wnr854t_pci __initdata = {
160 .setup = orion5x_pci_sys_setup,
161 .scan = orion5x_pci_sys_scan_bus,
162 .map_irq = wnr854t_pci_map_irq,
165 static int __init wnr854t_pci_init(void)
167 if (machine_is_wnr854t())
168 pci_common_init(&wnr854t_pci);
172 subsys_initcall(wnr854t_pci_init);
174 MACHINE_START(WNR854T, "Netgear WNR854T")
175 /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
176 .atag_offset = 0x100,
177 .init_machine = wnr854t_init,
178 .map_io = orion5x_map_io,
179 .init_early = orion5x_init_early,
180 .init_irq = orion5x_init_irq,
181 .init_time = orion5x_timer_init,
182 .fixup = tag_fixup_mem32,
183 .restart = orion5x_restart,