2 * OMAP2plus display device setup / initialization.
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Senthilvadivu Guruswamy
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/string.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
23 #include <linux/clk.h>
24 #include <linux/err.h>
25 #include <linux/delay.h>
27 #include <linux/of_platform.h>
28 #include <linux/slab.h>
29 #include <linux/mfd/syscon.h>
30 #include <linux/regmap.h>
32 #include <video/omapdss.h>
33 #include "omap_hwmod.h"
34 #include "omap_device.h"
44 #define DISPC_CONTROL 0x0040
45 #define DISPC_CONTROL2 0x0238
46 #define DISPC_CONTROL3 0x0848
47 #define DISPC_IRQSTATUS 0x0018
49 #define DSS_SYSCONFIG 0x10
50 #define DSS_SYSSTATUS 0x14
51 #define DSS_CONTROL 0x40
52 #define DSS_SDI_CONTROL 0x44
53 #define DSS_PLL_CONTROL 0x48
55 #define LCD_EN_MASK (0x1 << 0)
56 #define DIGIT_EN_MASK (0x1 << 1)
58 #define FRAMEDONE_IRQ_SHIFT 0
59 #define EVSYNC_EVEN_IRQ_SHIFT 2
60 #define EVSYNC_ODD_IRQ_SHIFT 3
61 #define FRAMEDONE2_IRQ_SHIFT 22
62 #define FRAMEDONE3_IRQ_SHIFT 30
63 #define FRAMEDONETV_IRQ_SHIFT 24
66 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
67 * reset before deciding that something has gone wrong
69 #define FRAMEDONE_IRQ_TIMEOUT 100
71 static struct platform_device omap_display_device = {
75 .platform_data = NULL,
79 struct omap_dss_hwmod_data {
85 static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = {
86 { "dss_core", "omapdss_dss", -1 },
87 { "dss_dispc", "omapdss_dispc", -1 },
88 { "dss_rfbi", "omapdss_rfbi", -1 },
89 { "dss_venc", "omapdss_venc", -1 },
92 static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = {
93 { "dss_core", "omapdss_dss", -1 },
94 { "dss_dispc", "omapdss_dispc", -1 },
95 { "dss_rfbi", "omapdss_rfbi", -1 },
96 { "dss_venc", "omapdss_venc", -1 },
97 { "dss_dsi1", "omapdss_dsi", 0 },
100 static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
101 { "dss_core", "omapdss_dss", -1 },
102 { "dss_dispc", "omapdss_dispc", -1 },
103 { "dss_rfbi", "omapdss_rfbi", -1 },
104 { "dss_dsi1", "omapdss_dsi", 0 },
105 { "dss_dsi2", "omapdss_dsi", 1 },
106 { "dss_hdmi", "omapdss_hdmi", -1 },
109 #define OMAP4_DSIPHY_SYSCON_OFFSET 0x78
111 static struct regmap *omap4_dsi_mux_syscon;
113 static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
115 u32 enable_mask, enable_shift;
116 u32 pipd_mask, pipd_shift;
120 enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
121 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
122 pipd_mask = OMAP4_DSI1_PIPD_MASK;
123 pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
124 } else if (dsi_id == 1) {
125 enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
126 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
127 pipd_mask = OMAP4_DSI2_PIPD_MASK;
128 pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
133 regmap_read(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, ®);
138 reg |= (lanes << enable_shift) & enable_mask;
139 reg |= (lanes << pipd_shift) & pipd_mask;
141 regmap_write(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, reg);
146 static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
148 if (cpu_is_omap44xx())
149 return omap4_dsi_mux_pads(dsi_id, lane_mask);
154 static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
156 if (cpu_is_omap44xx())
157 omap4_dsi_mux_pads(dsi_id, 0);
160 static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
162 return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput);
165 static struct platform_device *create_dss_pdev(const char *pdev_name,
166 int pdev_id, const char *oh_name, void *pdata, int pdata_len,
167 struct platform_device *parent)
169 struct platform_device *pdev;
170 struct omap_device *od;
171 struct omap_hwmod *ohs[1];
172 struct omap_hwmod *oh;
175 oh = omap_hwmod_lookup(oh_name);
177 pr_err("Could not look up %s\n", oh_name);
182 pdev = platform_device_alloc(pdev_name, pdev_id);
184 pr_err("Could not create pdev for %s\n", pdev_name);
190 pdev->dev.parent = &parent->dev;
193 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
195 dev_set_name(&pdev->dev, "%s", pdev->name);
198 od = omap_device_alloc(pdev, ohs, 1);
200 pr_err("Could not alloc omap_device for %s\n", pdev_name);
205 r = platform_device_add_data(pdev, pdata, pdata_len);
207 pr_err("Could not set pdata for %s\n", pdev_name);
211 r = omap_device_register(pdev);
213 pr_err("Could not register omap_device for %s\n", pdev_name);
223 static struct platform_device *create_simple_dss_pdev(const char *pdev_name,
224 int pdev_id, void *pdata, int pdata_len,
225 struct platform_device *parent)
227 struct platform_device *pdev;
230 pdev = platform_device_alloc(pdev_name, pdev_id);
232 pr_err("Could not create pdev for %s\n", pdev_name);
238 pdev->dev.parent = &parent->dev;
241 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
243 dev_set_name(&pdev->dev, "%s", pdev->name);
245 r = platform_device_add_data(pdev, pdata, pdata_len);
247 pr_err("Could not set pdata for %s\n", pdev_name);
251 r = platform_device_add(pdev);
253 pr_err("Could not register platform_device for %s\n", pdev_name);
263 static enum omapdss_version __init omap_display_get_version(void)
265 if (cpu_is_omap24xx())
266 return OMAPDSS_VER_OMAP24xx;
267 else if (cpu_is_omap3630())
268 return OMAPDSS_VER_OMAP3630;
269 else if (cpu_is_omap34xx()) {
270 if (soc_is_am35xx()) {
271 return OMAPDSS_VER_AM35xx;
273 if (omap_rev() < OMAP3430_REV_ES3_0)
274 return OMAPDSS_VER_OMAP34xx_ES1;
276 return OMAPDSS_VER_OMAP34xx_ES3;
278 } else if (omap_rev() == OMAP4430_REV_ES1_0)
279 return OMAPDSS_VER_OMAP4430_ES1;
280 else if (omap_rev() == OMAP4430_REV_ES2_0 ||
281 omap_rev() == OMAP4430_REV_ES2_1 ||
282 omap_rev() == OMAP4430_REV_ES2_2)
283 return OMAPDSS_VER_OMAP4430_ES2;
284 else if (cpu_is_omap44xx())
285 return OMAPDSS_VER_OMAP4;
286 else if (soc_is_omap54xx())
287 return OMAPDSS_VER_OMAP5;
288 else if (soc_is_am43xx())
289 return OMAPDSS_VER_AM43xx;
291 return OMAPDSS_VER_UNKNOWN;
294 int __init omap_display_init(struct omap_dss_board_info *board_data)
297 struct platform_device *pdev;
299 const struct omap_dss_hwmod_data *curr_dss_hwmod;
300 struct platform_device *dss_pdev;
301 enum omapdss_version ver;
303 /* create omapdss device */
305 ver = omap_display_get_version();
307 if (ver == OMAPDSS_VER_UNKNOWN) {
308 pr_err("DSS not supported on this SoC\n");
312 board_data->version = ver;
313 board_data->dsi_enable_pads = omap_dsi_enable_pads;
314 board_data->dsi_disable_pads = omap_dsi_disable_pads;
315 board_data->set_min_bus_tput = omap_dss_set_min_bus_tput;
317 omap_display_device.dev.platform_data = board_data;
319 r = platform_device_register(&omap_display_device);
321 pr_err("Unable to register omapdss device\n");
325 /* create devices for dss hwmods */
327 if (cpu_is_omap24xx()) {
328 curr_dss_hwmod = omap2_dss_hwmod_data;
329 oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
330 } else if (cpu_is_omap34xx()) {
331 curr_dss_hwmod = omap3_dss_hwmod_data;
332 oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
334 curr_dss_hwmod = omap4_dss_hwmod_data;
335 oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
339 * First create the pdev for dss_core, which is used as a parent device
340 * by the other dss pdevs. Note: dss_core has to be the first item in
343 dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name,
344 curr_dss_hwmod[0].id,
345 curr_dss_hwmod[0].oh_name,
346 board_data, sizeof(*board_data),
349 if (IS_ERR(dss_pdev)) {
350 pr_err("Could not build omap_device for %s\n",
351 curr_dss_hwmod[0].oh_name);
353 return PTR_ERR(dss_pdev);
356 for (i = 1; i < oh_count; i++) {
357 pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name,
358 curr_dss_hwmod[i].id,
359 curr_dss_hwmod[i].oh_name,
360 board_data, sizeof(*board_data),
364 pr_err("Could not build omap_device for %s\n",
365 curr_dss_hwmod[i].oh_name);
367 return PTR_ERR(pdev);
371 /* Create devices for DPI and SDI */
373 pdev = create_simple_dss_pdev("omapdss_dpi", 0,
374 board_data, sizeof(*board_data), dss_pdev);
376 pr_err("Could not build platform_device for omapdss_dpi\n");
377 return PTR_ERR(pdev);
380 if (cpu_is_omap34xx()) {
381 pdev = create_simple_dss_pdev("omapdss_sdi", 0,
382 board_data, sizeof(*board_data), dss_pdev);
384 pr_err("Could not build platform_device for omapdss_sdi\n");
385 return PTR_ERR(pdev);
389 /* create DRM device */
392 pr_err("Unable to register omapdrm device\n");
396 /* create vrfb device */
397 r = omap_init_vrfb();
399 pr_err("Unable to register omapvrfb device\n");
403 /* create FB device */
406 pr_err("Unable to register omapfb device\n");
410 /* create V4L2 display device */
411 r = omap_init_vout();
413 pr_err("Unable to register omap_vout device\n");
420 static void dispc_disable_outputs(void)
423 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
425 struct omap_dss_dispc_dev_attr *da;
426 struct omap_hwmod *oh;
428 oh = omap_hwmod_lookup("dss_dispc");
430 WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
435 pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
439 da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
441 /* store value of LCDENABLE and DIGITENABLE bits */
442 v = omap_hwmod_read(oh, DISPC_CONTROL);
443 lcd_en = v & LCD_EN_MASK;
444 digit_en = v & DIGIT_EN_MASK;
446 /* store value of LCDENABLE for LCD2 */
447 if (da->manager_count > 2) {
448 v = omap_hwmod_read(oh, DISPC_CONTROL2);
449 lcd2_en = v & LCD_EN_MASK;
452 /* store value of LCDENABLE for LCD3 */
453 if (da->manager_count > 3) {
454 v = omap_hwmod_read(oh, DISPC_CONTROL3);
455 lcd3_en = v & LCD_EN_MASK;
458 if (!(lcd_en | digit_en | lcd2_en | lcd3_en))
459 return; /* no managers currently enabled */
462 * If any manager was enabled, we need to disable it before
463 * DSS clocks are disabled or DISPC module is reset
466 irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;
469 if (da->has_framedonetv_irq) {
470 irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
472 irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
473 1 << EVSYNC_ODD_IRQ_SHIFT;
478 irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
480 irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT;
483 * clear any previous FRAMEDONE, FRAMEDONETV,
484 * EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
486 omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
488 /* disable LCD and TV managers */
489 v = omap_hwmod_read(oh, DISPC_CONTROL);
490 v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
491 omap_hwmod_write(v, oh, DISPC_CONTROL);
493 /* disable LCD2 manager */
494 if (da->manager_count > 2) {
495 v = omap_hwmod_read(oh, DISPC_CONTROL2);
497 omap_hwmod_write(v, oh, DISPC_CONTROL2);
500 /* disable LCD3 manager */
501 if (da->manager_count > 3) {
502 v = omap_hwmod_read(oh, DISPC_CONTROL3);
504 omap_hwmod_write(v, oh, DISPC_CONTROL3);
508 while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
511 if (i > FRAMEDONE_IRQ_TIMEOUT) {
512 pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
519 int omap_dss_reset(struct omap_hwmod *oh)
521 struct omap_hwmod_opt_clk *oc;
525 if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
526 pr_err("dss_core: hwmod data doesn't contain reset data\n");
530 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
532 clk_prepare_enable(oc->_clk);
534 dispc_disable_outputs();
536 /* clear SDI registers */
537 if (cpu_is_omap3430()) {
538 omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
539 omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
543 * clear DSS_CONTROL register to switch DSS clock sources to
546 omap_hwmod_write(0x0, oh, DSS_CONTROL);
548 omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
549 & SYSS_RESETDONE_MASK),
550 MAX_MODULE_SOFTRESET_WAIT, c);
552 if (c == MAX_MODULE_SOFTRESET_WAIT)
553 pr_warn("dss_core: waiting for reset to finish failed\n");
555 pr_debug("dss_core: softreset done\n");
557 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
559 clk_disable_unprepare(oc->_clk);
561 r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
566 void __init omapdss_early_init_of(void)
571 struct device_node * __init omapdss_find_dss_of_node(void)
573 struct device_node *node;
575 node = of_find_compatible_node(NULL, NULL, "ti,omap2-dss");
579 node = of_find_compatible_node(NULL, NULL, "ti,omap3-dss");
583 node = of_find_compatible_node(NULL, NULL, "ti,omap4-dss");
587 node = of_find_compatible_node(NULL, NULL, "ti,omap5-dss");
594 int __init omapdss_init_of(void)
597 enum omapdss_version ver;
598 struct device_node *node;
599 struct platform_device *pdev;
601 static struct omap_dss_board_info board_data = {
602 .dsi_enable_pads = omap_dsi_enable_pads,
603 .dsi_disable_pads = omap_dsi_disable_pads,
604 .set_min_bus_tput = omap_dss_set_min_bus_tput,
607 /* only create dss helper devices if dss is enabled in the .dts */
609 node = omapdss_find_dss_of_node();
613 if (!of_device_is_available(node))
616 ver = omap_display_get_version();
618 if (ver == OMAPDSS_VER_UNKNOWN) {
619 pr_err("DSS not supported on this SoC\n");
623 pdev = of_find_device_by_node(node);
626 pr_err("Unable to find DSS platform device\n");
630 r = of_platform_populate(node, NULL, NULL, &pdev->dev);
632 pr_err("Unable to populate DSS submodule devices\n");
636 board_data.version = ver;
638 omap_display_device.dev.platform_data = &board_data;
640 r = platform_device_register(&omap_display_device);
642 pr_err("Unable to register omapdss device\n");
646 /* create DRM device */
649 pr_err("Unable to register omapdrm device\n");
653 /* create vrfb device */
654 r = omap_init_vrfb();
656 pr_err("Unable to register omapvrfb device\n");
660 /* create FB device */
663 pr_err("Unable to register omapfb device\n");
667 /* create V4L2 display device */
668 r = omap_init_vout();
670 pr_err("Unable to register omap_vout device\n");
674 /* add DSI info for omap4 */
675 node = of_find_node_by_name(NULL, "omap4_padconf_global");
677 omap4_dsi_mux_syscon = syscon_node_to_regmap(node);