2 * linux/arch/arm/kernel/entry-armv.S
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Low-level vector interface routines
14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
15 * that causes it to save wrong values... Be aware!
18 #include <asm/assembler.h>
19 #include <asm/memory.h>
20 #include <asm/glue-df.h>
21 #include <asm/glue-pf.h>
22 #include <asm/vfpmacros.h>
23 #ifndef CONFIG_MULTI_IRQ_HANDLER
24 #include <mach/entry-macro.S>
26 #include <asm/thread_notify.h>
27 #include <asm/unwind.h>
28 #include <asm/unistd.h>
30 #include <asm/system_info.h>
32 #include "entry-header.S"
33 #include <asm/entry-macro-multi.S>
34 #include <asm/probes.h>
40 #ifdef CONFIG_MULTI_IRQ_HANDLER
41 ldr r1, =handle_arch_irq
46 arch_irq_handler_default
52 @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5
56 ldr pc, [ip, #PROCESSOR_PABT_FUNC]
65 @ Call the processor-specific abort handler:
68 @ r4 - aborted context pc
69 @ r5 - aborted context psr
71 @ The abort handler must return the aborted address in r0, and
72 @ the fault status register in r1. r9 must be preserved.
77 ldr pc, [ip, #PROCESSOR_DABT_FUNC]
84 .section .kprobes.text,"ax",%progbits
90 * Invalid mode handlers
92 .macro inv_entry, reason
93 sub sp, sp, #S_FRAME_SIZE
94 ARM( stmib sp, {r1 - lr} )
95 THUMB( stmia sp, {r0 - r12} )
96 THUMB( str sp, [sp, #S_SP] )
97 THUMB( str lr, [sp, #S_LR] )
102 inv_entry BAD_PREFETCH
104 ENDPROC(__pabt_invalid)
109 ENDPROC(__dabt_invalid)
114 ENDPROC(__irq_invalid)
117 inv_entry BAD_UNDEFINSTR
120 @ XXX fall through to common_invalid
124 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
130 add r0, sp, #S_PC @ here for interlock avoidance
131 mov r7, #-1 @ "" "" "" ""
132 str r4, [sp] @ save preserved r0
133 stmia r0, {r5 - r7} @ lr_<exception>,
134 @ cpsr_<exception>, "old_r0"
138 ENDPROC(__und_invalid)
144 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
145 #define SPFIX(code...) code
147 #define SPFIX(code...)
150 .macro svc_entry, stack_hole=0, trace=1
152 UNWIND(.save {r0 - pc} )
153 sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
154 #ifdef CONFIG_THUMB2_KERNEL
155 SPFIX( str r0, [sp] ) @ temporarily saved
157 SPFIX( tst r0, #4 ) @ test original stack alignment
158 SPFIX( ldr r0, [sp] ) @ restored
162 SPFIX( subeq sp, sp, #4 )
166 add r7, sp, #S_SP - 4 @ here for interlock avoidance
167 mov r6, #-1 @ "" "" "" ""
168 add r2, sp, #(S_FRAME_SIZE + \stack_hole - 4)
169 SPFIX( addeq r2, r2, #4 )
170 str r3, [sp, #-4]! @ save the "real" r0 copied
171 @ from the exception stack
176 @ We are now ready to fill in the remaining blanks on the stack:
180 @ r4 - lr_<exception>, already fixed up for correct return/restart
181 @ r5 - spsr_<exception>
182 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
187 #ifdef CONFIG_TRACE_IRQFLAGS
188 bl trace_hardirqs_off
198 THUMB( ldr r5, [sp, #S_PSR] ) @ potentially updated CPSR
199 svc_exit r5 @ return from exception
208 #ifdef CONFIG_PREEMPT
210 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
211 teq r8, #0 @ if preempt count != 0
212 bne 1f @ return from exeption
213 ldr r0, [tsk, #TI_FLAGS] @ get flags
214 tst r0, #_TIF_NEED_RESCHED @ if NEED_RESCHED is set
215 blne svc_preempt @ preempt!
217 ldr r8, [tsk, #TI_PREEMPT_LAZY] @ get preempt lazy count
218 teq r8, #0 @ if preempt lazy count != 0
219 movne r0, #0 @ force flags to 0
220 tst r0, #_TIF_NEED_RESCHED_LAZY
225 svc_exit r5, irq = 1 @ return from exception
231 #ifdef CONFIG_PREEMPT
234 1: bl preempt_schedule_irq @ irq en/disable is done inside
235 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
236 tst r0, #_TIF_NEED_RESCHED
238 tst r0, #_TIF_NEED_RESCHED_LAZY
244 @ Correct the PC such that it is pointing at the instruction
245 @ which caused the fault. If the faulting instruction was ARM
246 @ the PC will be pointing at the next instruction, and have to
247 @ subtract 4. Otherwise, it is Thumb, and the PC will be
248 @ pointing at the second half of the Thumb instruction. We
249 @ have to subtract 2.
258 #ifdef CONFIG_KPROBES
259 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
260 @ it obviously needs free stack space which then will belong to
262 svc_entry MAX_STACK_SIZE
267 @ call emulation code, which returns using r9 if it has emulated
268 @ the instruction, or the more conventional lr if we are to treat
269 @ this as a real undefined instruction
273 #ifndef CONFIG_THUMB2_KERNEL
277 ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2
278 cmp r0, #0xe800 @ 32-bit instruction if xx >= 0
280 ldrh r9, [r4] @ bottom 16 bits
283 orr r0, r9, r0, lsl #16
285 adr r9, BSYM(__und_svc_finish)
289 mov r1, #4 @ PC correction to apply
291 mov r0, sp @ struct pt_regs *regs
295 ldr r5, [sp, #S_PSR] @ Get SVC cpsr
296 svc_exit r5 @ return from exception
305 svc_exit r5 @ return from exception
312 mov r0, sp @ struct pt_regs *regs
329 * Abort mode handlers
333 @ Taking a FIQ in abort mode is similar to taking a FIQ in SVC mode
334 @ and reuses the same macros. However in abort mode we must also
335 @ save/restore lr_abt and spsr_abt to make nested aborts safe.
341 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
342 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
343 THUMB( msr cpsr_c, r0 )
344 mov r1, lr @ Save lr_abt
345 mrs r2, spsr @ Save spsr_abt, abort is now safe
346 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
347 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
348 THUMB( msr cpsr_c, r0 )
351 add r0, sp, #8 @ struct pt_regs *regs
355 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
356 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
357 THUMB( msr cpsr_c, r0 )
358 mov lr, r1 @ Restore lr_abt, abort is unsafe
359 msr spsr_cxsf, r2 @ Restore spsr_abt
360 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
361 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
362 THUMB( msr cpsr_c, r0 )
371 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
374 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
375 #error "sizeof(struct pt_regs) must be a multiple of 8"
378 .macro usr_entry, trace=1
380 UNWIND(.cantunwind ) @ don't unwind the user space
381 sub sp, sp, #S_FRAME_SIZE
382 ARM( stmib sp, {r1 - r12} )
383 THUMB( stmia sp, {r0 - r12} )
385 ATRAP( mrc p15, 0, r7, c1, c0, 0)
386 ATRAP( ldr r8, .LCcralign)
389 add r0, sp, #S_PC @ here for interlock avoidance
390 mov r6, #-1 @ "" "" "" ""
392 str r3, [sp] @ save the "real" r0 copied
393 @ from the exception stack
395 ATRAP( ldr r8, [r8, #0])
398 @ We are now ready to fill in the remaining blanks on the stack:
400 @ r4 - lr_<exception>, already fixed up for correct return/restart
401 @ r5 - spsr_<exception>
402 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
404 @ Also, separately save sp_usr and lr_usr
407 ARM( stmdb r0, {sp, lr}^ )
408 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
410 @ Enable the alignment trap while in kernel mode
412 ATRAP( mcrne p15, 0, r8, c1, c0, 0)
415 @ Clear FP to mark the first stack frame
420 #ifdef CONFIG_IRQSOFF_TRACER
421 bl trace_hardirqs_off
423 ct_user_exit save = 0
427 .macro kuser_cmpxchg_check
428 #if !defined(CONFIG_CPU_32v6K) && defined(CONFIG_KUSER_HELPERS) && \
429 !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
431 #warning "NPTL on non MMU needs fixing"
433 @ Make sure our user space atomic helper is restarted
434 @ if it was interrupted in a critical region. Here we
435 @ perform a quick test inline since it should be false
436 @ 99.9999% of the time. The rest is done out of line.
438 blhs kuser_cmpxchg64_fixup
460 b ret_to_user_from_irq
473 @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the
474 @ faulting instruction depending on Thumb mode.
475 @ r3 = regs->ARM_cpsr
477 @ The emulation code returns using r9 if it has emulated the
478 @ instruction, or the more conventional lr if we are to treat
479 @ this as a real undefined instruction
481 adr r9, BSYM(ret_from_exception)
483 @ IRQs must be enabled before attempting to read the instruction from
484 @ user space since that could cause a page/translation fault if the
485 @ page table was modified by another CPU.
488 tst r3, #PSR_T_BIT @ Thumb mode?
490 sub r4, r2, #4 @ ARM instr at LR - 4
492 ARM_BE8(rev r0, r0) @ little endian instruction
494 @ r0 = 32-bit ARM instruction which caused the exception
495 @ r2 = PC value for the following instruction (:= regs->ARM_pc)
496 @ r4 = PC value for the faulting instruction
497 @ lr = 32-bit undefined instruction function
498 adr lr, BSYM(__und_usr_fault_32)
503 sub r4, r2, #2 @ First half of thumb instr at LR - 2
504 #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
506 * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms
507 * can never be supported in a single kernel, this code is not applicable at
508 * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be
509 * made about .arch directives.
511 #if __LINUX_ARM_ARCH__ < 7
512 /* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */
513 #define NEED_CPU_ARCHITECTURE
514 ldr r5, .LCcpu_architecture
516 cmp r5, #CPU_ARCH_ARMv7
517 blo __und_usr_fault_16 @ 16bit undefined instruction
519 * The following code won't get run unless the running CPU really is v7, so
520 * coding round the lack of ldrht on older arches is pointless. Temporarily
521 * override the assembler target arch with the minimum required instead:
526 ARM_BE8(rev16 r5, r5) @ little endian instruction
527 cmp r5, #0xe800 @ 32bit instruction if xx != 0
528 blo __und_usr_fault_16 @ 16bit undefined instruction
530 ARM_BE8(rev16 r0, r0) @ little endian instruction
531 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
532 str r2, [sp, #S_PC] @ it's a 2x16bit instr, update
533 orr r0, r0, r5, lsl #16
534 adr lr, BSYM(__und_usr_fault_32)
535 @ r0 = the two 16-bit Thumb instructions which caused the exception
536 @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc)
537 @ r4 = PC value for the first 16-bit Thumb instruction
538 @ lr = 32bit undefined instruction function
540 #if __LINUX_ARM_ARCH__ < 7
541 /* If the target arch was overridden, change it back: */
542 #ifdef CONFIG_CPU_32v6K
547 #endif /* __LINUX_ARM_ARCH__ < 7 */
548 #else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */
555 * The out of line fixup for the ldrt instructions above.
557 .pushsection .text.fixup, "ax"
559 4: str r4, [sp, #S_PC] @ retry current instruction
562 .pushsection __ex_table,"a"
564 #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
571 * Check whether the instruction is a co-processor instruction.
572 * If yes, we need to call the relevant co-processor handler.
574 * Note that we don't do a full check here for the co-processor
575 * instructions; all instructions with bit 27 set are well
576 * defined. The only instructions that should fault are the
577 * co-processor instructions. However, we have to watch out
578 * for the ARM6/ARM7 SWI bug.
580 * NEON is a special case that has to be handled here. Not all
581 * NEON instructions are co-processor instructions, so we have
582 * to make a special case of checking for them. Plus, there's
583 * five groups of them, so we have a table of mask/opcode pairs
584 * to check against, and if any match then we branch off into the
587 * Emulators may wish to make use of the following registers:
588 * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb)
589 * r2 = PC value to resume execution after successful emulation
590 * r9 = normal "successful" return address
591 * r10 = this threads thread_info structure
592 * lr = unrecognised instruction return address
593 * IRQs enabled, FIQs enabled.
596 @ Fall-through from Thumb-2 __und_usr
599 get_thread_info r10 @ get current thread
600 adr r6, .LCneon_thumb_opcodes
604 get_thread_info r10 @ get current thread
606 adr r6, .LCneon_arm_opcodes
607 2: ldr r5, [r6], #4 @ mask value
608 ldr r7, [r6], #4 @ opcode bits matching in mask
609 cmp r5, #0 @ end mask?
612 cmp r8, r7 @ NEON instruction?
615 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
616 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
617 b do_vfp @ let VFP handler handle this
620 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
621 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
623 and r8, r0, #0x00000f00 @ mask out CP number
624 THUMB( lsr r8, r8, #8 )
626 add r6, r10, #TI_USED_CP
627 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[]
628 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[]
630 @ Test if we need to give access to iWMMXt coprocessors
631 ldr r5, [r10, #TI_FLAGS]
632 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
633 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
634 bcs iwmmxt_task_enable
636 ARM( add pc, pc, r8, lsr #6 )
637 THUMB( lsl r8, r8, #2 )
642 W(b) do_fpe @ CP#1 (FPE)
643 W(b) do_fpe @ CP#2 (FPE)
646 b crunch_task_enable @ CP#4 (MaverickCrunch)
647 b crunch_task_enable @ CP#5 (MaverickCrunch)
648 b crunch_task_enable @ CP#6 (MaverickCrunch)
658 W(b) do_vfp @ CP#10 (VFP)
659 W(b) do_vfp @ CP#11 (VFP)
661 ret.w lr @ CP#10 (VFP)
662 ret.w lr @ CP#11 (VFP)
666 ret.w lr @ CP#14 (Debug)
667 ret.w lr @ CP#15 (Control)
669 #ifdef NEED_CPU_ARCHITECTURE
672 .word __cpu_architecture
679 .word 0xfe000000 @ mask
680 .word 0xf2000000 @ opcode
682 .word 0xff100000 @ mask
683 .word 0xf4000000 @ opcode
685 .word 0x00000000 @ mask
686 .word 0x00000000 @ opcode
688 .LCneon_thumb_opcodes:
689 .word 0xef000000 @ mask
690 .word 0xef000000 @ opcode
692 .word 0xff100000 @ mask
693 .word 0xf9000000 @ opcode
695 .word 0x00000000 @ mask
696 .word 0x00000000 @ opcode
701 add r10, r10, #TI_FPSTATE @ r10 = workspace
702 ldr pc, [r4] @ Call FP module USR entry point
705 * The FP module is called with these registers set:
708 * r9 = normal "successful" return address
710 * lr = unrecognised FP instruction return address
728 adr lr, BSYM(ret_from_exception)
730 ENDPROC(__und_usr_fault_32)
731 ENDPROC(__und_usr_fault_16)
741 * This is the return code to user mode for abort handlers
743 ENTRY(ret_from_exception)
751 ENDPROC(ret_from_exception)
757 mov r0, sp @ struct pt_regs *regs
760 restore_user_regs fast = 0, offset = 0
765 * Register switch for ARMv3 and ARMv4 processors
766 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
767 * previous and next are guaranteed not to be the same.
772 add ip, r1, #TI_CPU_SAVE
773 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
774 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
775 THUMB( str sp, [ip], #4 )
776 THUMB( str lr, [ip], #4 )
777 ldr r4, [r2, #TI_TP_VALUE]
778 ldr r5, [r2, #TI_TP_VALUE + 4]
779 #ifdef CONFIG_CPU_USE_DOMAINS
780 ldr r6, [r2, #TI_CPU_DOMAIN]
782 switch_tls r1, r4, r5, r3, r7
783 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
784 ldr r7, [r2, #TI_TASK]
785 ldr r8, =__stack_chk_guard
786 ldr r7, [r7, #TSK_STACK_CANARY]
788 #ifdef CONFIG_CPU_USE_DOMAINS
789 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
792 add r4, r2, #TI_CPU_SAVE
793 ldr r0, =thread_notify_head
794 mov r1, #THREAD_NOTIFY_SWITCH
795 bl atomic_notifier_call_chain
796 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
801 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
802 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
803 THUMB( ldr sp, [ip], #4 )
804 THUMB( ldr pc, [ip] )
813 * Each segment is 32-byte aligned and will be moved to the top of the high
814 * vector page. New segments (if ever needed) must be added in front of
815 * existing ones. This mechanism should be used only for things that are
816 * really small and justified, and not be abused freely.
818 * See Documentation/arm/kernel_user_helpers.txt for formal definitions.
823 #ifdef CONFIG_ARM_THUMB
830 .macro kuser_pad, sym, size
832 .rept 4 - (. - \sym) & 3
836 .rept (\size - (. - \sym)) / 4
841 #ifdef CONFIG_KUSER_HELPERS
843 .globl __kuser_helper_start
844 __kuser_helper_start:
847 * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular
848 * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point.
851 __kuser_cmpxchg64: @ 0xffff0f60
853 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
856 * Poor you. No fast solution possible...
857 * The kernel itself must perform the operation.
858 * A special ghost syscall is used for that (see traps.c).
861 ldr r7, 1f @ it's 20 bits
862 swi __ARM_NR_cmpxchg64
864 1: .word __ARM_NR_cmpxchg64
866 #elif defined(CONFIG_CPU_32v6K)
868 stmfd sp!, {r4, r5, r6, r7}
869 ldrd r4, r5, [r0] @ load old val
870 ldrd r6, r7, [r1] @ load new val
872 1: ldrexd r0, r1, [r2] @ load current val
873 eors r3, r0, r4 @ compare with oldval (1)
874 eoreqs r3, r1, r5 @ compare with oldval (2)
875 strexdeq r3, r6, r7, [r2] @ store newval if eq
876 teqeq r3, #1 @ success?
877 beq 1b @ if no then retry
879 rsbs r0, r3, #0 @ set returned val and C flag
880 ldmfd sp!, {r4, r5, r6, r7}
883 #elif !defined(CONFIG_SMP)
888 * The only thing that can break atomicity in this cmpxchg64
889 * implementation is either an IRQ or a data abort exception
890 * causing another process/thread to be scheduled in the middle of
891 * the critical sequence. The same strategy as for cmpxchg is used.
893 stmfd sp!, {r4, r5, r6, lr}
894 ldmia r0, {r4, r5} @ load old val
895 ldmia r1, {r6, lr} @ load new val
896 1: ldmia r2, {r0, r1} @ load current val
897 eors r3, r0, r4 @ compare with oldval (1)
898 eoreqs r3, r1, r5 @ compare with oldval (2)
899 2: stmeqia r2, {r6, lr} @ store newval if eq
900 rsbs r0, r3, #0 @ set return val and C flag
901 ldmfd sp!, {r4, r5, r6, pc}
904 kuser_cmpxchg64_fixup:
905 @ Called from kuser_cmpxchg_fixup.
906 @ r4 = address of interrupted insn (must be preserved).
907 @ sp = saved regs. r7 and r8 are clobbered.
908 @ 1b = first critical insn, 2b = last critical insn.
909 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
911 sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64)))
913 rsbcss r8, r8, #(2b - 1b)
914 strcs r7, [sp, #S_PC]
915 #if __LINUX_ARM_ARCH__ < 6
916 bcc kuser_cmpxchg32_fixup
922 #warning "NPTL on non MMU needs fixing"
929 #error "incoherent kernel configuration"
932 kuser_pad __kuser_cmpxchg64, 64
934 __kuser_memory_barrier: @ 0xffff0fa0
938 kuser_pad __kuser_memory_barrier, 32
940 __kuser_cmpxchg: @ 0xffff0fc0
942 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
945 * Poor you. No fast solution possible...
946 * The kernel itself must perform the operation.
947 * A special ghost syscall is used for that (see traps.c).
950 ldr r7, 1f @ it's 20 bits
953 1: .word __ARM_NR_cmpxchg
955 #elif __LINUX_ARM_ARCH__ < 6
960 * The only thing that can break atomicity in this cmpxchg
961 * implementation is either an IRQ or a data abort exception
962 * causing another process/thread to be scheduled in the middle
963 * of the critical sequence. To prevent this, code is added to
964 * the IRQ and data abort exception handlers to set the pc back
965 * to the beginning of the critical section if it is found to be
966 * within that critical section (see kuser_cmpxchg_fixup).
968 1: ldr r3, [r2] @ load current val
969 subs r3, r3, r0 @ compare with oldval
970 2: streq r1, [r2] @ store newval if eq
971 rsbs r0, r3, #0 @ set return val and C flag
975 kuser_cmpxchg32_fixup:
976 @ Called from kuser_cmpxchg_check macro.
977 @ r4 = address of interrupted insn (must be preserved).
978 @ sp = saved regs. r7 and r8 are clobbered.
979 @ 1b = first critical insn, 2b = last critical insn.
980 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
982 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
984 rsbcss r8, r8, #(2b - 1b)
985 strcs r7, [sp, #S_PC]
990 #warning "NPTL on non MMU needs fixing"
1001 strexeq r3, r1, [r2]
1005 /* beware -- each __kuser slot must be 8 instructions max */
1006 ALT_SMP(b __kuser_memory_barrier)
1011 kuser_pad __kuser_cmpxchg, 32
1013 __kuser_get_tls: @ 0xffff0fe0
1014 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
1016 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
1017 kuser_pad __kuser_get_tls, 16
1019 .word 0 @ 0xffff0ff0 software TLS value, then
1020 .endr @ pad up to __kuser_helper_version
1022 __kuser_helper_version: @ 0xffff0ffc
1023 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
1025 .globl __kuser_helper_end
1035 * This code is copied to 0xffff1000 so we can use branches in the
1036 * vectors, rather than ldr's. Note that this code must not exceed
1039 * Common stub entry macro:
1040 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1042 * SP points to a minimal amount of processor-private memory, the address
1043 * of which is copied into r0 for the mode specific abort handler.
1045 .macro vector_stub, name, mode, correction=0
1050 sub lr, lr, #\correction
1054 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
1057 stmia sp, {r0, lr} @ save r0, lr
1059 str lr, [sp, #8] @ save spsr
1062 @ Prepare for SVC32 mode. IRQs remain disabled.
1065 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
1069 @ the branch table must immediately follow this code
1073 THUMB( ldr lr, [r0, lr, lsl #2] )
1075 ARM( ldr lr, [pc, lr, lsl #2] )
1076 movs pc, lr @ branch to handler in SVC mode
1077 ENDPROC(vector_\name)
1080 @ handler addresses follow this label
1084 .section .stubs, "ax", %progbits
1086 @ This must be the first word
1090 ARM( swi SYS_ERROR0 )
1096 * Interrupt dispatcher
1098 vector_stub irq, IRQ_MODE, 4
1100 .long __irq_usr @ 0 (USR_26 / USR_32)
1101 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
1102 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
1103 .long __irq_svc @ 3 (SVC_26 / SVC_32)
1104 .long __irq_invalid @ 4
1105 .long __irq_invalid @ 5
1106 .long __irq_invalid @ 6
1107 .long __irq_invalid @ 7
1108 .long __irq_invalid @ 8
1109 .long __irq_invalid @ 9
1110 .long __irq_invalid @ a
1111 .long __irq_invalid @ b
1112 .long __irq_invalid @ c
1113 .long __irq_invalid @ d
1114 .long __irq_invalid @ e
1115 .long __irq_invalid @ f
1118 * Data abort dispatcher
1119 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1121 vector_stub dabt, ABT_MODE, 8
1123 .long __dabt_usr @ 0 (USR_26 / USR_32)
1124 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
1125 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
1126 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
1127 .long __dabt_invalid @ 4
1128 .long __dabt_invalid @ 5
1129 .long __dabt_invalid @ 6
1130 .long __dabt_invalid @ 7
1131 .long __dabt_invalid @ 8
1132 .long __dabt_invalid @ 9
1133 .long __dabt_invalid @ a
1134 .long __dabt_invalid @ b
1135 .long __dabt_invalid @ c
1136 .long __dabt_invalid @ d
1137 .long __dabt_invalid @ e
1138 .long __dabt_invalid @ f
1141 * Prefetch abort dispatcher
1142 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1144 vector_stub pabt, ABT_MODE, 4
1146 .long __pabt_usr @ 0 (USR_26 / USR_32)
1147 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
1148 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
1149 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
1150 .long __pabt_invalid @ 4
1151 .long __pabt_invalid @ 5
1152 .long __pabt_invalid @ 6
1153 .long __pabt_invalid @ 7
1154 .long __pabt_invalid @ 8
1155 .long __pabt_invalid @ 9
1156 .long __pabt_invalid @ a
1157 .long __pabt_invalid @ b
1158 .long __pabt_invalid @ c
1159 .long __pabt_invalid @ d
1160 .long __pabt_invalid @ e
1161 .long __pabt_invalid @ f
1164 * Undef instr entry dispatcher
1165 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1167 vector_stub und, UND_MODE
1169 .long __und_usr @ 0 (USR_26 / USR_32)
1170 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1171 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1172 .long __und_svc @ 3 (SVC_26 / SVC_32)
1173 .long __und_invalid @ 4
1174 .long __und_invalid @ 5
1175 .long __und_invalid @ 6
1176 .long __und_invalid @ 7
1177 .long __und_invalid @ 8
1178 .long __und_invalid @ 9
1179 .long __und_invalid @ a
1180 .long __und_invalid @ b
1181 .long __und_invalid @ c
1182 .long __und_invalid @ d
1183 .long __und_invalid @ e
1184 .long __und_invalid @ f
1188 /*=============================================================================
1189 * Address exception handler
1190 *-----------------------------------------------------------------------------
1191 * These aren't too critical.
1192 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1198 /*=============================================================================
1200 *-----------------------------------------------------------------------------
1201 * Handle a FIQ using the SVC stack allowing FIQ act like NMI on x86
1204 vector_stub fiq, FIQ_MODE, 4
1206 .long __fiq_usr @ 0 (USR_26 / USR_32)
1207 .long __fiq_svc @ 1 (FIQ_26 / FIQ_32)
1208 .long __fiq_svc @ 2 (IRQ_26 / IRQ_32)
1209 .long __fiq_svc @ 3 (SVC_26 / SVC_32)
1223 .globl vector_fiq_offset
1224 .equ vector_fiq_offset, vector_fiq
1226 .section .vectors, "ax", %progbits
1230 W(ldr) pc, __vectors_start + 0x1000
1233 W(b) vector_addrexcptn
1243 #ifdef CONFIG_MULTI_IRQ_HANDLER
1244 .globl handle_arch_irq