2 * SAMSUNG EXYNOS5420 SoC device tree source
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
8 * EXYNOS5420 based board files can include this file and provide
9 * values for board specfic bindings.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <dt-bindings/clock/exynos5420.h>
17 #include "exynos5.dtsi"
18 #include "exynos5420-pinctrl.dtsi"
20 #include <dt-bindings/clock/exynos-audss-clk.h>
23 compatible = "samsung,exynos5420", "samsung,exynos5";
29 pinctrl0 = &pinctrl_0;
30 pinctrl1 = &pinctrl_1;
31 pinctrl2 = &pinctrl_2;
32 pinctrl3 = &pinctrl_3;
33 pinctrl4 = &pinctrl_4;
50 usbdrdphy0 = &usbdrd_phy0;
51 usbdrdphy1 = &usbdrd_phy1;
60 compatible = "arm,cortex-a15";
62 clock-frequency = <1800000000>;
63 cci-control-port = <&cci_control1>;
68 compatible = "arm,cortex-a15";
70 clock-frequency = <1800000000>;
71 cci-control-port = <&cci_control1>;
76 compatible = "arm,cortex-a15";
78 clock-frequency = <1800000000>;
79 cci-control-port = <&cci_control1>;
84 compatible = "arm,cortex-a15";
86 clock-frequency = <1800000000>;
87 cci-control-port = <&cci_control1>;
92 compatible = "arm,cortex-a7";
94 clock-frequency = <1000000000>;
95 cci-control-port = <&cci_control0>;
100 compatible = "arm,cortex-a7";
102 clock-frequency = <1000000000>;
103 cci-control-port = <&cci_control0>;
108 compatible = "arm,cortex-a7";
110 clock-frequency = <1000000000>;
111 cci-control-port = <&cci_control0>;
116 compatible = "arm,cortex-a7";
118 clock-frequency = <1000000000>;
119 cci-control-port = <&cci_control0>;
124 compatible = "arm,cci-400";
125 #address-cells = <1>;
127 reg = <0x10d20000 0x1000>;
128 ranges = <0x0 0x10d20000 0x6000>;
130 cci_control0: slave-if@4000 {
131 compatible = "arm,cci-400-ctrl-if";
132 interface-type = "ace";
133 reg = <0x4000 0x1000>;
135 cci_control1: slave-if@5000 {
136 compatible = "arm,cci-400-ctrl-if";
137 interface-type = "ace";
138 reg = <0x5000 0x1000>;
143 compatible = "mmio-sram";
144 reg = <0x02020000 0x54000>;
145 #address-cells = <1>;
147 ranges = <0 0x02020000 0x54000>;
150 compatible = "samsung,exynos4210-sysram";
155 compatible = "samsung,exynos4210-sysram-ns";
156 reg = <0x53000 0x1000>;
160 clock: clock-controller@10010000 {
161 compatible = "samsung,exynos5420-clock";
162 reg = <0x10010000 0x30000>;
166 clock_audss: audss-clock-controller@3810000 {
167 compatible = "samsung,exynos5420-audss-clock";
168 reg = <0x03810000 0x0C>;
170 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
171 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
172 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
175 mfc: codec@11000000 {
176 compatible = "samsung,mfc-v7";
177 reg = <0x11000000 0x10000>;
178 interrupts = <0 96 0>;
179 clocks = <&clock CLK_MFC>;
181 power-domains = <&mfc_pd>;
184 mmc_0: mmc@12200000 {
185 compatible = "samsung,exynos5420-dw-mshc-smu";
186 interrupts = <0 75 0>;
187 #address-cells = <1>;
189 reg = <0x12200000 0x2000>;
190 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
191 clock-names = "biu", "ciu";
196 mmc_1: mmc@12210000 {
197 compatible = "samsung,exynos5420-dw-mshc-smu";
198 interrupts = <0 76 0>;
199 #address-cells = <1>;
201 reg = <0x12210000 0x2000>;
202 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
203 clock-names = "biu", "ciu";
208 mmc_2: mmc@12220000 {
209 compatible = "samsung,exynos5420-dw-mshc";
210 interrupts = <0 77 0>;
211 #address-cells = <1>;
213 reg = <0x12220000 0x1000>;
214 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
215 clock-names = "biu", "ciu";
221 compatible = "samsung,exynos4210-mct";
222 reg = <0x101C0000 0x800>;
223 interrupt-controller;
224 #interrupt-cells = <1>;
225 interrupt-parent = <&mct_map>;
226 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
227 <8>, <9>, <10>, <11>;
228 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
229 clock-names = "fin_pll", "mct";
232 #interrupt-cells = <1>;
233 #address-cells = <0>;
235 interrupt-map = <0 &combiner 23 3>,
250 gsc_pd: power-domain@10044000 {
251 compatible = "samsung,exynos4210-pd";
252 reg = <0x10044000 0x20>;
253 #power-domain-cells = <0>;
254 clocks = <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
255 clock-names = "asb0", "asb1";
258 isp_pd: power-domain@10044020 {
259 compatible = "samsung,exynos4210-pd";
260 reg = <0x10044020 0x20>;
261 #power-domain-cells = <0>;
264 mfc_pd: power-domain@10044060 {
265 compatible = "samsung,exynos4210-pd";
266 reg = <0x10044060 0x20>;
267 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
268 <&clock CLK_MOUT_USER_ACLK333>;
269 clock-names = "oscclk", "pclk0", "clk0";
270 #power-domain-cells = <0>;
273 msc_pd: power-domain@10044120 {
274 compatible = "samsung,exynos4210-pd";
275 reg = <0x10044120 0x20>;
276 #power-domain-cells = <0>;
279 disp_pd: power-domain@100440C0 {
280 compatible = "samsung,exynos4210-pd";
281 reg = <0x100440C0 0x20>;
282 #power-domain-cells = <0>;
283 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK200>,
284 <&clock CLK_MOUT_USER_ACLK200_DISP1>,
285 <&clock CLK_MOUT_SW_ACLK300>,
286 <&clock CLK_MOUT_USER_ACLK300_DISP1>,
287 <&clock CLK_MOUT_SW_ACLK400>,
288 <&clock CLK_MOUT_USER_ACLK400_DISP1>,
289 <&clock CLK_FIMD1>, <&clock CLK_MIXER>;
290 clock-names = "oscclk", "pclk0", "clk0",
291 "pclk1", "clk1", "pclk2", "clk2",
295 pinctrl_0: pinctrl@13400000 {
296 compatible = "samsung,exynos5420-pinctrl";
297 reg = <0x13400000 0x1000>;
298 interrupts = <0 45 0>;
300 wakeup-interrupt-controller {
301 compatible = "samsung,exynos4210-wakeup-eint";
302 interrupt-parent = <&gic>;
303 interrupts = <0 32 0>;
307 pinctrl_1: pinctrl@13410000 {
308 compatible = "samsung,exynos5420-pinctrl";
309 reg = <0x13410000 0x1000>;
310 interrupts = <0 78 0>;
313 pinctrl_2: pinctrl@14000000 {
314 compatible = "samsung,exynos5420-pinctrl";
315 reg = <0x14000000 0x1000>;
316 interrupts = <0 46 0>;
319 pinctrl_3: pinctrl@14010000 {
320 compatible = "samsung,exynos5420-pinctrl";
321 reg = <0x14010000 0x1000>;
322 interrupts = <0 50 0>;
325 pinctrl_4: pinctrl@03860000 {
326 compatible = "samsung,exynos5420-pinctrl";
327 reg = <0x03860000 0x1000>;
328 interrupts = <0 47 0>;
332 clocks = <&clock CLK_RTC>;
334 interrupt-parent = <&pmu_system_controller>;
339 #address-cells = <1>;
341 compatible = "arm,amba-bus";
342 interrupt-parent = <&gic>;
345 adma: adma@03880000 {
346 compatible = "arm,pl330", "arm,primecell";
347 reg = <0x03880000 0x1000>;
348 interrupts = <0 110 0>;
349 clocks = <&clock_audss EXYNOS_ADMA>;
350 clock-names = "apb_pclk";
353 #dma-requests = <16>;
356 pdma0: pdma@121A0000 {
357 compatible = "arm,pl330", "arm,primecell";
358 reg = <0x121A0000 0x1000>;
359 interrupts = <0 34 0>;
360 clocks = <&clock CLK_PDMA0>;
361 clock-names = "apb_pclk";
364 #dma-requests = <32>;
367 pdma1: pdma@121B0000 {
368 compatible = "arm,pl330", "arm,primecell";
369 reg = <0x121B0000 0x1000>;
370 interrupts = <0 35 0>;
371 clocks = <&clock CLK_PDMA1>;
372 clock-names = "apb_pclk";
375 #dma-requests = <32>;
378 mdma0: mdma@10800000 {
379 compatible = "arm,pl330", "arm,primecell";
380 reg = <0x10800000 0x1000>;
381 interrupts = <0 33 0>;
382 clocks = <&clock CLK_MDMA0>;
383 clock-names = "apb_pclk";
389 mdma1: mdma@11C10000 {
390 compatible = "arm,pl330", "arm,primecell";
391 reg = <0x11C10000 0x1000>;
392 interrupts = <0 124 0>;
393 clocks = <&clock CLK_MDMA1>;
394 clock-names = "apb_pclk";
399 * MDMA1 can support both secure and non-secure
400 * AXI transactions. When this is enabled in the kernel
401 * for boards that run in secure mode, we are getting
402 * imprecise external aborts causing the kernel to oops.
409 compatible = "samsung,exynos5420-i2s";
410 reg = <0x03830000 0x100>;
414 dma-names = "tx", "rx", "tx-sec";
415 clocks = <&clock_audss EXYNOS_I2S_BUS>,
416 <&clock_audss EXYNOS_I2S_BUS>,
417 <&clock_audss EXYNOS_SCLK_I2S>;
418 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
419 samsung,idma-addr = <0x03000000>;
420 pinctrl-names = "default";
421 pinctrl-0 = <&i2s0_bus>;
426 compatible = "samsung,exynos5420-i2s";
427 reg = <0x12D60000 0x100>;
430 dma-names = "tx", "rx";
431 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
432 clock-names = "iis", "i2s_opclk0";
433 pinctrl-names = "default";
434 pinctrl-0 = <&i2s1_bus>;
439 compatible = "samsung,exynos5420-i2s";
440 reg = <0x12D70000 0x100>;
443 dma-names = "tx", "rx";
444 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
445 clock-names = "iis", "i2s_opclk0";
446 pinctrl-names = "default";
447 pinctrl-0 = <&i2s2_bus>;
451 spi_0: spi@12d20000 {
452 compatible = "samsung,exynos4210-spi";
453 reg = <0x12d20000 0x100>;
454 interrupts = <0 68 0>;
457 dma-names = "tx", "rx";
458 #address-cells = <1>;
460 pinctrl-names = "default";
461 pinctrl-0 = <&spi0_bus>;
462 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
463 clock-names = "spi", "spi_busclk0";
467 spi_1: spi@12d30000 {
468 compatible = "samsung,exynos4210-spi";
469 reg = <0x12d30000 0x100>;
470 interrupts = <0 69 0>;
473 dma-names = "tx", "rx";
474 #address-cells = <1>;
476 pinctrl-names = "default";
477 pinctrl-0 = <&spi1_bus>;
478 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
479 clock-names = "spi", "spi_busclk0";
483 spi_2: spi@12d40000 {
484 compatible = "samsung,exynos4210-spi";
485 reg = <0x12d40000 0x100>;
486 interrupts = <0 70 0>;
489 dma-names = "tx", "rx";
490 #address-cells = <1>;
492 pinctrl-names = "default";
493 pinctrl-0 = <&spi2_bus>;
494 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
495 clock-names = "spi", "spi_busclk0";
499 uart_0: serial@12C00000 {
500 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
501 clock-names = "uart", "clk_uart_baud0";
504 uart_1: serial@12C10000 {
505 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
506 clock-names = "uart", "clk_uart_baud0";
509 uart_2: serial@12C20000 {
510 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
511 clock-names = "uart", "clk_uart_baud0";
514 uart_3: serial@12C30000 {
515 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
516 clock-names = "uart", "clk_uart_baud0";
520 compatible = "samsung,exynos4210-pwm";
521 reg = <0x12dd0000 0x100>;
522 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
524 clocks = <&clock CLK_PWM>;
525 clock-names = "timers";
528 dp_phy: video-phy@10040728 {
529 compatible = "samsung,exynos5420-dp-video-phy";
530 samsung,pmu-syscon = <&pmu_system_controller>;
534 dp: dp-controller@145B0000 {
535 clocks = <&clock CLK_DP1>;
539 power-domains = <&disp_pd>;
542 mipi_phy: video-phy@10040714 {
543 compatible = "samsung,s5pv210-mipi-video-phy";
544 reg = <0x10040714 12>;
549 compatible = "samsung,exynos5410-mipi-dsi";
550 reg = <0x14500000 0x10000>;
551 interrupts = <0 82 0>;
552 phys = <&mipi_phy 1>;
554 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
555 clock-names = "bus_clk", "pll_clk";
556 #address-cells = <1>;
561 fimd: fimd@14400000 {
562 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
563 clock-names = "sclk_fimd", "fimd";
564 power-domains = <&disp_pd>;
568 compatible = "samsung,exynos-adc-v2";
569 reg = <0x12D10000 0x100>;
570 interrupts = <0 106 0>;
571 clocks = <&clock CLK_TSADC>;
573 #io-channel-cells = <1>;
575 samsung,syscon-phandle = <&pmu_system_controller>;
579 i2c_0: i2c@12C60000 {
580 compatible = "samsung,s3c2440-i2c";
581 reg = <0x12C60000 0x100>;
582 interrupts = <0 56 0>;
583 #address-cells = <1>;
585 clocks = <&clock CLK_I2C0>;
587 pinctrl-names = "default";
588 pinctrl-0 = <&i2c0_bus>;
589 samsung,sysreg-phandle = <&sysreg_system_controller>;
593 i2c_1: i2c@12C70000 {
594 compatible = "samsung,s3c2440-i2c";
595 reg = <0x12C70000 0x100>;
596 interrupts = <0 57 0>;
597 #address-cells = <1>;
599 clocks = <&clock CLK_I2C1>;
601 pinctrl-names = "default";
602 pinctrl-0 = <&i2c1_bus>;
603 samsung,sysreg-phandle = <&sysreg_system_controller>;
607 i2c_2: i2c@12C80000 {
608 compatible = "samsung,s3c2440-i2c";
609 reg = <0x12C80000 0x100>;
610 interrupts = <0 58 0>;
611 #address-cells = <1>;
613 clocks = <&clock CLK_I2C2>;
615 pinctrl-names = "default";
616 pinctrl-0 = <&i2c2_bus>;
617 samsung,sysreg-phandle = <&sysreg_system_controller>;
621 i2c_3: i2c@12C90000 {
622 compatible = "samsung,s3c2440-i2c";
623 reg = <0x12C90000 0x100>;
624 interrupts = <0 59 0>;
625 #address-cells = <1>;
627 clocks = <&clock CLK_I2C3>;
629 pinctrl-names = "default";
630 pinctrl-0 = <&i2c3_bus>;
631 samsung,sysreg-phandle = <&sysreg_system_controller>;
635 hsi2c_4: i2c@12CA0000 {
636 compatible = "samsung,exynos5-hsi2c";
637 reg = <0x12CA0000 0x1000>;
638 interrupts = <0 60 0>;
639 #address-cells = <1>;
641 pinctrl-names = "default";
642 pinctrl-0 = <&i2c4_hs_bus>;
643 clocks = <&clock CLK_USI0>;
644 clock-names = "hsi2c";
648 hsi2c_5: i2c@12CB0000 {
649 compatible = "samsung,exynos5-hsi2c";
650 reg = <0x12CB0000 0x1000>;
651 interrupts = <0 61 0>;
652 #address-cells = <1>;
654 pinctrl-names = "default";
655 pinctrl-0 = <&i2c5_hs_bus>;
656 clocks = <&clock CLK_USI1>;
657 clock-names = "hsi2c";
661 hsi2c_6: i2c@12CC0000 {
662 compatible = "samsung,exynos5-hsi2c";
663 reg = <0x12CC0000 0x1000>;
664 interrupts = <0 62 0>;
665 #address-cells = <1>;
667 pinctrl-names = "default";
668 pinctrl-0 = <&i2c6_hs_bus>;
669 clocks = <&clock CLK_USI2>;
670 clock-names = "hsi2c";
674 hsi2c_7: i2c@12CD0000 {
675 compatible = "samsung,exynos5-hsi2c";
676 reg = <0x12CD0000 0x1000>;
677 interrupts = <0 63 0>;
678 #address-cells = <1>;
680 pinctrl-names = "default";
681 pinctrl-0 = <&i2c7_hs_bus>;
682 clocks = <&clock CLK_USI3>;
683 clock-names = "hsi2c";
687 hsi2c_8: i2c@12E00000 {
688 compatible = "samsung,exynos5-hsi2c";
689 reg = <0x12E00000 0x1000>;
690 interrupts = <0 87 0>;
691 #address-cells = <1>;
693 pinctrl-names = "default";
694 pinctrl-0 = <&i2c8_hs_bus>;
695 clocks = <&clock CLK_USI4>;
696 clock-names = "hsi2c";
700 hsi2c_9: i2c@12E10000 {
701 compatible = "samsung,exynos5-hsi2c";
702 reg = <0x12E10000 0x1000>;
703 interrupts = <0 88 0>;
704 #address-cells = <1>;
706 pinctrl-names = "default";
707 pinctrl-0 = <&i2c9_hs_bus>;
708 clocks = <&clock CLK_USI5>;
709 clock-names = "hsi2c";
713 hsi2c_10: i2c@12E20000 {
714 compatible = "samsung,exynos5-hsi2c";
715 reg = <0x12E20000 0x1000>;
716 interrupts = <0 203 0>;
717 #address-cells = <1>;
719 pinctrl-names = "default";
720 pinctrl-0 = <&i2c10_hs_bus>;
721 clocks = <&clock CLK_USI6>;
722 clock-names = "hsi2c";
726 hdmi: hdmi@14530000 {
727 compatible = "samsung,exynos5420-hdmi";
728 reg = <0x14530000 0x70000>;
729 interrupts = <0 95 0>;
730 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
731 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
732 <&clock CLK_MOUT_HDMI>;
733 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
734 "sclk_hdmiphy", "mout_hdmi";
736 samsung,syscon-phandle = <&pmu_system_controller>;
738 power-domains = <&disp_pd>;
741 hdmiphy: hdmiphy@145D0000 {
742 reg = <0x145D0000 0x20>;
745 mixer: mixer@14450000 {
746 compatible = "samsung,exynos5420-mixer";
747 reg = <0x14450000 0x10000>;
748 interrupts = <0 94 0>;
749 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
750 <&clock CLK_SCLK_HDMI>;
751 clock-names = "mixer", "hdmi", "sclk_hdmi";
752 power-domains = <&disp_pd>;
755 gsc_0: video-scaler@13e00000 {
756 compatible = "samsung,exynos5-gsc";
757 reg = <0x13e00000 0x1000>;
758 interrupts = <0 85 0>;
759 clocks = <&clock CLK_GSCL0>;
760 clock-names = "gscl";
761 power-domains = <&gsc_pd>;
764 gsc_1: video-scaler@13e10000 {
765 compatible = "samsung,exynos5-gsc";
766 reg = <0x13e10000 0x1000>;
767 interrupts = <0 86 0>;
768 clocks = <&clock CLK_GSCL1>;
769 clock-names = "gscl";
770 power-domains = <&gsc_pd>;
773 pmu_system_controller: system-controller@10040000 {
774 compatible = "samsung,exynos5420-pmu", "syscon";
775 reg = <0x10040000 0x5000>;
776 clock-names = "clkout16";
777 clocks = <&clock CLK_FIN_PLL>;
779 interrupt-controller;
780 #interrupt-cells = <3>;
781 interrupt-parent = <&gic>;
784 sysreg_system_controller: syscon@10050000 {
785 compatible = "samsung,exynos5-sysreg", "syscon";
786 reg = <0x10050000 0x5000>;
789 tmu_cpu0: tmu@10060000 {
790 compatible = "samsung,exynos5420-tmu";
791 reg = <0x10060000 0x100>;
792 interrupts = <0 65 0>;
793 clocks = <&clock CLK_TMU>;
794 clock-names = "tmu_apbif";
795 #include "exynos4412-tmu-sensor-conf.dtsi"
798 tmu_cpu1: tmu@10064000 {
799 compatible = "samsung,exynos5420-tmu";
800 reg = <0x10064000 0x100>;
801 interrupts = <0 183 0>;
802 clocks = <&clock CLK_TMU>;
803 clock-names = "tmu_apbif";
804 #include "exynos4412-tmu-sensor-conf.dtsi"
807 tmu_cpu2: tmu@10068000 {
808 compatible = "samsung,exynos5420-tmu-ext-triminfo";
809 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
810 interrupts = <0 184 0>;
811 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
812 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
813 #include "exynos4412-tmu-sensor-conf.dtsi"
816 tmu_cpu3: tmu@1006c000 {
817 compatible = "samsung,exynos5420-tmu-ext-triminfo";
818 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
819 interrupts = <0 185 0>;
820 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
821 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
822 #include "exynos4412-tmu-sensor-conf.dtsi"
825 tmu_gpu: tmu@100a0000 {
826 compatible = "samsung,exynos5420-tmu-ext-triminfo";
827 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
828 interrupts = <0 215 0>;
829 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
830 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
831 #include "exynos4412-tmu-sensor-conf.dtsi"
835 cpu0_thermal: cpu0-thermal {
836 thermal-sensors = <&tmu_cpu0>;
837 #include "exynos5420-trip-points.dtsi"
839 cpu1_thermal: cpu1-thermal {
840 thermal-sensors = <&tmu_cpu1>;
841 #include "exynos5420-trip-points.dtsi"
843 cpu2_thermal: cpu2-thermal {
844 thermal-sensors = <&tmu_cpu2>;
845 #include "exynos5420-trip-points.dtsi"
847 cpu3_thermal: cpu3-thermal {
848 thermal-sensors = <&tmu_cpu3>;
849 #include "exynos5420-trip-points.dtsi"
851 gpu_thermal: gpu-thermal {
852 thermal-sensors = <&tmu_gpu>;
853 #include "exynos5420-trip-points.dtsi"
857 watchdog: watchdog@101D0000 {
858 compatible = "samsung,exynos5420-wdt";
859 reg = <0x101D0000 0x100>;
860 interrupts = <0 42 0>;
861 clocks = <&clock CLK_WDT>;
862 clock-names = "watchdog";
863 samsung,syscon-phandle = <&pmu_system_controller>;
867 compatible = "samsung,exynos4210-secss";
868 reg = <0x10830000 0x10000>;
869 interrupts = <0 112 0>;
870 clocks = <&clock CLK_SSS>;
871 clock-names = "secss";
874 usbdrd3_0: usb@12000000 {
875 compatible = "samsung,exynos5250-dwusb3";
876 clocks = <&clock CLK_USBD300>;
877 clock-names = "usbdrd30";
878 #address-cells = <1>;
882 usbdrd_dwc3_0: dwc3 {
883 compatible = "snps,dwc3";
884 reg = <0x12000000 0x10000>;
885 interrupts = <0 72 0>;
886 phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
887 phy-names = "usb2-phy", "usb3-phy";
891 usbdrd_phy0: phy@12100000 {
892 compatible = "samsung,exynos5420-usbdrd-phy";
893 reg = <0x12100000 0x100>;
894 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
895 clock-names = "phy", "ref";
896 samsung,pmu-syscon = <&pmu_system_controller>;
900 usbdrd3_1: usb@12400000 {
901 compatible = "samsung,exynos5250-dwusb3";
902 clocks = <&clock CLK_USBD301>;
903 clock-names = "usbdrd30";
904 #address-cells = <1>;
908 usbdrd_dwc3_1: dwc3 {
909 compatible = "snps,dwc3";
910 reg = <0x12400000 0x10000>;
911 interrupts = <0 73 0>;
912 phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
913 phy-names = "usb2-phy", "usb3-phy";
917 usbdrd_phy1: phy@12500000 {
918 compatible = "samsung,exynos5420-usbdrd-phy";
919 reg = <0x12500000 0x100>;
920 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
921 clock-names = "phy", "ref";
922 samsung,pmu-syscon = <&pmu_system_controller>;
926 usbhost2: usb@12110000 {
927 compatible = "samsung,exynos4210-ehci";
928 reg = <0x12110000 0x100>;
929 interrupts = <0 71 0>;
931 clocks = <&clock CLK_USBH20>;
932 clock-names = "usbhost";
933 #address-cells = <1>;
937 phys = <&usb2_phy 1>;
941 usbhost1: usb@12120000 {
942 compatible = "samsung,exynos4210-ohci";
943 reg = <0x12120000 0x100>;
944 interrupts = <0 71 0>;
946 clocks = <&clock CLK_USBH20>;
947 clock-names = "usbhost";
948 #address-cells = <1>;
952 phys = <&usb2_phy 1>;
956 usb2_phy: phy@12130000 {
957 compatible = "samsung,exynos5250-usb2-phy";
958 reg = <0x12130000 0x100>;
959 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
960 clock-names = "phy", "ref";
962 samsung,sysreg-phandle = <&sysreg_system_controller>;
963 samsung,pmureg-phandle = <&pmu_system_controller>;