kernel/arch/arc/boot/dts/axc003_idu.dtsi

   1 /*
   2  * Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com)
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /*
  10  * Device tree for AXC003 CPU card: HS38x2 (Dual Core) with IDU intc
  11  */
  12
  13 / {
  14         compatible = "snps,arc";
  15         clock-frequency = <90000000>;
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         cpu_card {
  20                 compatible = "simple-bus";
  21                 #address-cells = <1>;
  22                 #size-cells = <1>;
  23
  24                 ranges = <0x00000000 0xf0000000 0x10000000>;
  25
  26                 cpu_intc: archs-intc@cpu {
  27                         compatible = "snps,archs-intc";
  28                         interrupt-controller;
  29                         #interrupt-cells = <1>;
  30                 };
  31
  32                 idu_intc: idu-interrupt-controller {
  33                         compatible = "snps,archs-idu-intc";
  34                         interrupt-controller;
  35                         interrupt-parent = <&cpu_intc>;
  36
  37                         /*
  38                          * <hwirq  distribution>
  39                          * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
  40                          */
  41                         #interrupt-cells = <2>;
  42
  43                         /*
  44                          * upstream irqs to core intc - downstream these are
  45                          * "COMMON" irq 0,1..
  46                          */
  47                         interrupts = <24 25>;
  48                 };
  49
  50                 /*
  51                  * this GPIO block ORs all interrupts on CPU card (creg,..)
  52                  * to uplink only 1 IRQ to ARC core intc
  53                  */
  54                 dw-apb-gpio@0x2000 {
  55                         compatible = "snps,dw-apb-gpio";
  56                         reg = < 0x2000 0x80 >;
  57                         #address-cells = <1>;
  58                         #size-cells = <0>;
  59
  60                         ictl_intc: gpio-controller@0 {
  61                                 compatible = "snps,dw-apb-gpio-port";
  62                                 gpio-controller;
  63                                 #gpio-cells = <2>;
  64                                 snps,nr-gpios = <30>;
  65                                 reg = <0>;
  66                                 interrupt-controller;
  67                                 #interrupt-cells = <2>;
  68                                 interrupt-parent = <&idu_intc>;
  69
  70                                 /*
  71                                  * cmn irq 1 -> cpu irq 25
  72                                  * Distribute to cpu0 only
  73                                  */
  74                                 interrupts = <1 1>;
  75                         };
  76                 };
  77
  78                 debug_uart: dw-apb-uart@0x5000 {
  79                         compatible = "snps,dw-apb-uart";
  80                         reg = <0x5000 0x100>;
  81                         clock-frequency = <33333000>;
  82                         interrupt-parent = <&ictl_intc>;
  83                         interrupts = <2 4>;
  84                         baud = <115200>;
  85                         reg-shift = <2>;
  86                         reg-io-width = <4>;
  87                 };
  88
  89                 arcpct0: pct {
  90                         compatible = "snps,archs-pct";
  91                         #interrupt-cells = <1>;
  92                         interrupt-parent = <&cpu_intc>;
  93                         interrupts = <20>;
  94                 };
  95         };
  96
  97         /*
  98          * This INTC is actually connected to DW APB GPIO
  99          * which acts as a wire between MB INTC and CPU INTC.
 100          * GPIO INTC is configured in platform init code
 101          * and here we mimic direct connection from MB INTC to
 102          * CPU INTC, thus we set "interrupts = <0 1>" instead of
 103          * "interrupts = <12>"
 104          *
 105          * This intc actually resides on MB, but we move it here to
 106          * avoid duplicating the MB dtsi file given that IRQ from
 107          * this intc to cpu intc are different for axs101 and axs103
 108          */
 109         mb_intc: dw-apb-ictl@0xe0012000 {
 110                 #interrupt-cells = <1>;
 111                 compatible = "snps,dw-apb-ictl";
 112                 reg = < 0xe0012000 0x200 >;
 113                 interrupt-controller;
 114                 interrupt-parent = <&idu_intc>;
 115                 interrupts = <0 1>;     /* cmn irq 0 -> cpu irq 24
 116                                            distribute to cpu0 only */
 117         };
 118
 119         memory {
 120                 #address-cells = <1>;
 121                 #size-cells = <1>;
 122                 ranges = <0x00000000 0x80000000 0x40000000>;
 123                 device_type = "memory";
 124                 reg = <0x80000000 0x20000000>;  /* 512MiB */
 125         };
 126 };