2 // Copyright (c) 2017 Intel Corporation
4 // Licensed under the Apache License, Version 2.0 (the "License");
5 // you may not use this file except in compliance with the License.
6 // You may obtain a copy of the License at
8 // http://www.apache.org/licenses/LICENSE-2.0
10 // Unless required by applicable law or agreed to in writing, software
11 // distributed under the License is distributed on an "AS IS" BASIS,
12 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 // See the License for the specific language governing permissions and
14 // limitations under the License.
17 #ifndef __INCLUDE_VNF_COMMON_H__
18 #define __INCLUDE_VNF_COMMON_H__
20 #include <rte_pipeline.h>
21 #include <rte_ether.h>
23 #define MBUF_HDR_ROOM 256
24 #define ETH_HDR_SIZE 14
25 #define IP_HDR_SRC_ADR_OFST 12
26 #define IP_HDR_DST_ADR_OFST 16
27 #define IP_HDR_PROTOCOL_OFST 9
28 #define IP_HDR_SIZE 20
29 #define IPV6_HDR_SRC_ADR_OFST 8
30 #define IPV6_HDR_DST_ADR_OFST 24
31 #define IPV6_HDR_PROTOCOL_OFST 6
32 #define IPV6_HDR_SIZE 40
34 #define ETH_TYPE_ARP 0x0806
35 #define ETH_TYPE_IPV4 0x0800
37 #define IP_PROTOCOL_ICMP 1
38 #define IP_PROTOCOL_TCP 6
39 #define IP_PROTOCOL_UDP 17
41 #define ETH_TYPE_IPV6 0x86DD
42 #define IP_PROTOCOL_ICMPV6 58
47 #ifndef PIPELINE_MAX_PORT_IN
48 #define PIPELINE_MAX_PORT_IN 64
51 #define RTE_PIPELINE_MAX_NAME_SZ 124
53 #define INVALID_DESTIF 255
59 void show_ports_info(void);
60 void trim(char *input);
61 uint8_t get_in_port_dir(uint8_t in_port_id);
62 uint8_t is_phy_port_privte(uint16_t phy_port);
63 uint32_t get_prv_to_pub_port(uint32_t *ip_addr, uint8_t type);
64 uint32_t get_pub_to_prv_port(uint32_t *ip_addr, uint8_t type);
66 static inline void drop_pkt(uint32_t pkt_num, uint64_t *mask)
68 *mask ^= 1LLU << pkt_num;
71 extern uint8_t in_port_dir_a[PIPELINE_MAX_PORT_IN];
72 extern uint8_t prv_to_pub_map[PIPELINE_MAX_PORT_IN];
73 extern uint8_t pub_to_prv_map[PIPELINE_MAX_PORT_IN];
74 extern uint8_t prv_in_port_a[PIPELINE_MAX_PORT_IN];
76 extern uint32_t link_hw_addr_array_idx;
79 /* Input parameters */
80 struct rte_port_in_ops ops;
81 rte_pipeline_port_in_action_handler f_action;
85 /* The table to which this port is connected */
88 /* Handle to low-level port */
91 /* List of enabled ports */
92 struct rte_port_in *next;
95 uint64_t n_pkts_dropped_by_ah;
99 /* Input parameters */
100 struct rte_port_out_ops ops;
101 rte_pipeline_port_out_action_handler f_action;
104 /* Handle to low-level port */
108 uint64_t n_pkts_dropped_by_ah;
112 /* Input parameters */
113 struct rte_table_ops ops;
114 rte_pipeline_table_action_handler_hit f_action_hit;
115 rte_pipeline_table_action_handler_miss f_action_miss;
117 struct rte_pipeline_table_entry *default_entry;
120 uint32_t table_next_id;
121 uint32_t table_next_id_valid;
123 /* Handle to the low-level table object */
127 uint64_t n_pkts_dropped_by_lkp_hit_ah;
128 uint64_t n_pkts_dropped_by_lkp_miss_ah;
129 uint64_t n_pkts_dropped_lkp_hit;
130 uint64_t n_pkts_dropped_lkp_miss;
134 struct rte_pipeline {
135 /* Input parameters */
136 char name[RTE_PIPELINE_MAX_NAME_SZ];
138 uint32_t offset_port_id;
140 /* Internal tables */
141 struct rte_port_in ports_in[RTE_PIPELINE_PORT_IN_MAX];
142 struct rte_port_out ports_out[RTE_PIPELINE_PORT_OUT_MAX];
143 struct rte_table tables[RTE_PIPELINE_TABLE_MAX];
145 /* Occupancy of internal tables */
146 uint32_t num_ports_in;
147 uint32_t num_ports_out;
150 /* List of enabled ports */
151 uint64_t enabled_port_in_mask;
152 struct rte_port_in *port_in_next;
154 /* Pipeline run structures */
155 struct rte_mbuf *pkts[RTE_PORT_IN_BURST_SIZE_MAX];
156 struct rte_pipeline_table_entry *entries[RTE_PORT_IN_BURST_SIZE_MAX];
157 uint64_t action_mask0[RTE_PIPELINE_ACTIONS];
158 uint64_t action_mask1[RTE_PIPELINE_ACTIONS];
160 uint64_t n_pkts_ah_drop;
161 uint64_t pkts_drop_mask;
162 } __rte_cache_aligned;
164 /* RTE_ DPDK LIB structures to get HWQ & SWQ info */
165 struct rte_port_ethdev_writer {
166 struct rte_port_out_stats stats;
168 struct rte_mbuf *tx_buf[2 * RTE_PORT_IN_BURST_SIZE_MAX];
169 uint32_t tx_burst_sz;
170 uint16_t tx_buf_count;
175 struct rte_port_ethdev_reader {
176 struct rte_port_in_stats stats;
181 struct rte_port_ring_writer {
182 struct rte_port_out_stats stats;
184 struct rte_mbuf *tx_buf[2 * RTE_PORT_IN_BURST_SIZE_MAX];
185 struct rte_ring *ring;
186 uint32_t tx_burst_sz;
187 uint32_t tx_buf_count;
191 struct rte_port_ring_reader {
192 struct rte_port_in_stats stats;
194 struct rte_ring *ring;
197 uint8_t get_in_port_dir(uint8_t in_port_id);
198 uint8_t is_phy_port_privte(uint16_t phy_port);
199 uint8_t is_port_index_privte(uint16_t phy_port);