common/VIL/pipeline_passthrough/pipeline_passthrough_be.c

   1 /*
   2 // Copyright (c) 2017 Intel Corporation
   3 //
   4 // Licensed under the Apache License, Version 2.0 (the "License");
   5 // you may not use this file except in compliance with the License.
   6 // You may obtain a copy of the License at
   7 //
   8 //      http://www.apache.org/licenses/LICENSE-2.0
   9 //
  10 // Unless required by applicable law or agreed to in writing, software
  11 // distributed under the License is distributed on an "AS IS" BASIS,
  12 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13 // See the License for the specific language governing permissions and
  14 // limitations under the License.
  15 */
  16
  17 #include <string.h>
  18
  19 #include <rte_common.h>
  20 #include <rte_malloc.h>
  21 #include <rte_byteorder.h>
  22 #include <rte_table_stub.h>
  23 #include <rte_table_hash.h>
  24 #include <rte_pipeline.h>
  25
  26 #include "pipeline_passthrough_be.h"
  27 #include "pipeline_actions_common.h"
  28 #include "parser.h"
  29 #include "hash_func.h"
  30
  31 struct pipeline_passthrough {
  32         struct pipeline p;
  33         struct pipeline_passthrough_params params;
  34         rte_table_hash_op_hash f_hash;
  35 } __rte_cache_aligned;
  36
  37 static pipeline_msg_req_handler handlers[] = {
  38         [PIPELINE_MSG_REQ_PING] =
  39                 pipeline_msg_req_ping_handler,
  40         [PIPELINE_MSG_REQ_STATS_PORT_IN] =
  41                 pipeline_msg_req_stats_port_in_handler,
  42         [PIPELINE_MSG_REQ_STATS_PORT_OUT] =
  43                 pipeline_msg_req_stats_port_out_handler,
  44         [PIPELINE_MSG_REQ_STATS_TABLE] =
  45                 pipeline_msg_req_stats_table_handler,
  46         [PIPELINE_MSG_REQ_PORT_IN_ENABLE] =
  47                 pipeline_msg_req_port_in_enable_handler,
  48         [PIPELINE_MSG_REQ_PORT_IN_DISABLE] =
  49                 pipeline_msg_req_port_in_disable_handler,
  50         [PIPELINE_MSG_REQ_CUSTOM] =
  51                 pipeline_msg_req_invalid_handler,
  52 };
  53
  54 static inline __attribute__((always_inline)) void
  55 pkt_work(
  56         struct rte_mbuf *pkt,
  57         void *arg,
  58         uint32_t dma_size,
  59         uint32_t hash_enabled,
  60         uint32_t lb_hash,
  61         uint32_t port_out_pow2)
  62 {
  63         struct pipeline_passthrough *p = arg;
  64
  65         uint64_t *dma_dst = RTE_MBUF_METADATA_UINT64_PTR(pkt,
  66                 p->params.dma_dst_offset);
  67         uint64_t *dma_src = RTE_MBUF_METADATA_UINT64_PTR(pkt,
  68                 p->params.dma_src_offset);
  69         uint64_t *dma_mask = (uint64_t *) p->params.dma_src_mask;
  70         uint32_t *dma_hash = RTE_MBUF_METADATA_UINT32_PTR(pkt,
  71                 p->params.dma_hash_offset);
  72         uint32_t i;
  73
  74         /* Read (dma_src), compute (dma_dst), write (dma_dst) */
  75         for (i = 0; i < (dma_size / 8); i++)
  76                 dma_dst[i] = dma_src[i] & dma_mask[i];
  77
  78         /* Read (dma_dst), compute (hash), write (hash) */
  79         if (hash_enabled) {
  80                 uint32_t hash = p->f_hash(dma_dst, dma_size, 0);
  81                 *dma_hash = hash;
  82
  83                 if (lb_hash) {
  84                         uint32_t port_out;
  85
  86                         if (port_out_pow2)
  87                                 port_out
  88                                         = hash & (p->p.n_ports_out - 1);
  89                         else
  90                                 port_out
  91                                         = hash % p->p.n_ports_out;
  92
  93                         rte_pipeline_port_out_packet_insert(p->p.p,
  94                                 port_out, pkt);
  95                 }
  96         }
  97 }
  98
  99 static inline __attribute__((always_inline)) void
 100 pkt4_work(
 101         struct rte_mbuf **pkts,
 102         void *arg,
 103         uint32_t dma_size,
 104         uint32_t hash_enabled,
 105         uint32_t lb_hash,
 106         uint32_t port_out_pow2)
 107 {
 108         struct pipeline_passthrough *p = arg;
 109
 110         uint64_t *dma_dst0 = RTE_MBUF_METADATA_UINT64_PTR(pkts[0],
 111                 p->params.dma_dst_offset);
 112         uint64_t *dma_dst1 = RTE_MBUF_METADATA_UINT64_PTR(pkts[1],
 113                 p->params.dma_dst_offset);
 114         uint64_t *dma_dst2 = RTE_MBUF_METADATA_UINT64_PTR(pkts[2],
 115                 p->params.dma_dst_offset);
 116         uint64_t *dma_dst3 = RTE_MBUF_METADATA_UINT64_PTR(pkts[3],
 117                 p->params.dma_dst_offset);
 118
 119         uint64_t *dma_src0 = RTE_MBUF_METADATA_UINT64_PTR(pkts[0],
 120                 p->params.dma_src_offset);
 121         uint64_t *dma_src1 = RTE_MBUF_METADATA_UINT64_PTR(pkts[1],
 122                 p->params.dma_src_offset);
 123         uint64_t *dma_src2 = RTE_MBUF_METADATA_UINT64_PTR(pkts[2],
 124                 p->params.dma_src_offset);
 125         uint64_t *dma_src3 = RTE_MBUF_METADATA_UINT64_PTR(pkts[3],
 126                 p->params.dma_src_offset);
 127
 128         uint64_t *dma_mask = (uint64_t *) p->params.dma_src_mask;
 129
 130         uint32_t *dma_hash0 = RTE_MBUF_METADATA_UINT32_PTR(pkts[0],
 131                 p->params.dma_hash_offset);
 132         uint32_t *dma_hash1 = RTE_MBUF_METADATA_UINT32_PTR(pkts[1],
 133                 p->params.dma_hash_offset);
 134         uint32_t *dma_hash2 = RTE_MBUF_METADATA_UINT32_PTR(pkts[2],
 135                 p->params.dma_hash_offset);
 136         uint32_t *dma_hash3 = RTE_MBUF_METADATA_UINT32_PTR(pkts[3],
 137                 p->params.dma_hash_offset);
 138
 139         uint32_t i;
 140
 141         /* Read (dma_src), compute (dma_dst), write (dma_dst) */
 142         for (i = 0; i < (dma_size / 8); i++) {
 143                 dma_dst0[i] = dma_src0[i] & dma_mask[i];
 144                 dma_dst1[i] = dma_src1[i] & dma_mask[i];
 145                 dma_dst2[i] = dma_src2[i] & dma_mask[i];
 146                 dma_dst3[i] = dma_src3[i] & dma_mask[i];
 147         }
 148
 149         /* Read (dma_dst), compute (hash), write (hash) */
 150         if (hash_enabled) {
 151                 uint32_t hash0 = p->f_hash(dma_dst0, dma_size, 0);
 152                 uint32_t hash1 = p->f_hash(dma_dst1, dma_size, 0);
 153                 uint32_t hash2 = p->f_hash(dma_dst2, dma_size, 0);
 154                 uint32_t hash3 = p->f_hash(dma_dst3, dma_size, 0);
 155
 156                 *dma_hash0 = hash0;
 157                 *dma_hash1 = hash1;
 158                 *dma_hash2 = hash2;
 159                 *dma_hash3 = hash3;
 160
 161                 if (lb_hash) {
 162                         uint32_t port_out0, port_out1, port_out2, port_out3;
 163
 164                         if (port_out_pow2) {
 165                                 port_out0
 166                                         = hash0 & (p->p.n_ports_out - 1);
 167                                 port_out1
 168                                         = hash1 & (p->p.n_ports_out - 1);
 169                                 port_out2
 170                                         = hash2 & (p->p.n_ports_out - 1);
 171                                 port_out3
 172                                         = hash3 & (p->p.n_ports_out - 1);
 173                         } else {
 174                                 port_out0
 175                                         = hash0 % p->p.n_ports_out;
 176                                 port_out1
 177                                         = hash1 % p->p.n_ports_out;
 178                                 port_out2
 179                                         = hash2 % p->p.n_ports_out;
 180                                 port_out3
 181                                         = hash3 % p->p.n_ports_out;
 182                         }
 183                         rte_pipeline_port_out_packet_insert(p->p.p,
 184                                 port_out0, pkts[0]);
 185                         rte_pipeline_port_out_packet_insert(p->p.p,
 186                                 port_out1, pkts[1]);
 187                         rte_pipeline_port_out_packet_insert(p->p.p,
 188                                 port_out2, pkts[2]);
 189                         rte_pipeline_port_out_packet_insert(p->p.p,
 190                                 port_out3, pkts[3]);
 191                 }
 192         }
 193 }
 194
 195 #define PKT_WORK(dma_size, hash_enabled, lb_hash, port_pow2)    \
 196 static inline void                                              \
 197 pkt_work_size##dma_size##_hash##hash_enabled            \
 198         ##_lb##lb_hash##_pw##port_pow2(                 \
 199         struct rte_mbuf *pkt,                                   \
 200         void *arg)                                              \
 201 {                                                               \
 202         pkt_work(pkt, arg, dma_size, hash_enabled, lb_hash, port_pow2); \
 203 }
 204
 205 #define PKT4_WORK(dma_size, hash_enabled, lb_hash, port_pow2)   \
 206 static inline void                                              \
 207 pkt4_work_size##dma_size##_hash##hash_enabled                   \
 208         ##_lb##lb_hash##_pw##port_pow2(                 \
 209         struct rte_mbuf **pkts,                                 \
 210         void *arg)                                              \
 211 {                                                               \
 212         pkt4_work(pkts, arg, dma_size, hash_enabled, lb_hash, port_pow2); \
 213 }
 214
 215 #define port_in_ah(dma_size, hash_enabled, lb_hash, port_pow2)  \
 216 PKT_WORK(dma_size, hash_enabled, lb_hash, port_pow2)                    \
 217 PKT4_WORK(dma_size, hash_enabled, lb_hash, port_pow2)                   \
 218 PIPELINE_PORT_IN_AH(port_in_ah_size##dma_size##_hash    \
 219         ##hash_enabled##_lb##lb_hash##_pw##port_pow2,           \
 220         pkt_work_size##dma_size##_hash##hash_enabled            \
 221         ##_lb##lb_hash##_pw##port_pow2,                 \
 222         pkt4_work_size##dma_size##_hash##hash_enabled           \
 223         ##_lb##lb_hash##_pw##port_pow2)
 224
 225
 226 #define port_in_ah_lb(dma_size, hash_enabled, lb_hash, port_pow2) \
 227 PKT_WORK(dma_size, hash_enabled, lb_hash, port_pow2)            \
 228 PKT4_WORK(dma_size, hash_enabled, lb_hash, port_pow2)   \
 229 PIPELINE_PORT_IN_AH_HIJACK_ALL(                                         \
 230         port_in_ah_size##dma_size##_hash##hash_enabled          \
 231         ##_lb##lb_hash##_pw##port_pow2,                 \
 232         pkt_work_size##dma_size##_hash##hash_enabled            \
 233         ##_lb##lb_hash##_pw##port_pow2, \
 234         pkt4_work_size##dma_size##_hash##hash_enabled           \
 235         ##_lb##lb_hash##_pw##port_pow2)
 236
 237 /* Port in AH (dma_size, hash_enabled, lb_hash, port_pow2) */
 238
 239 port_in_ah(8, 0, 0, 0)
 240 port_in_ah(8, 1, 0, 0)
 241 port_in_ah_lb(8, 1, 1, 0)
 242 port_in_ah_lb(8, 1, 1, 1)
 243
 244 port_in_ah(16, 0, 0, 0)
 245 port_in_ah(16, 1, 0, 0)
 246 port_in_ah_lb(16, 1, 1, 0)
 247 port_in_ah_lb(16, 1, 1, 1)
 248
 249 port_in_ah(24, 0, 0, 0)
 250 port_in_ah(24, 1, 0, 0)
 251 port_in_ah_lb(24, 1, 1, 0)
 252 port_in_ah_lb(24, 1, 1, 1)
 253
 254 port_in_ah(32, 0, 0, 0)
 255 port_in_ah(32, 1, 0, 0)
 256 port_in_ah_lb(32, 1, 1, 0)
 257 port_in_ah_lb(32, 1, 1, 1)
 258
 259 port_in_ah(40, 0, 0, 0)
 260 port_in_ah(40, 1, 0, 0)
 261 port_in_ah_lb(40, 1, 1, 0)
 262 port_in_ah_lb(40, 1, 1, 1)
 263
 264 port_in_ah(48, 0, 0, 0)
 265 port_in_ah(48, 1, 0, 0)
 266 port_in_ah_lb(48, 1, 1, 0)
 267 port_in_ah_lb(48, 1, 1, 1)
 268
 269 port_in_ah(56, 0, 0, 0)
 270 port_in_ah(56, 1, 0, 0)
 271 port_in_ah_lb(56, 1, 1, 0)
 272 port_in_ah_lb(56, 1, 1, 1)
 273
 274 port_in_ah(64, 0, 0, 0)
 275 port_in_ah(64, 1, 0, 0)
 276 port_in_ah_lb(64, 1, 1, 0)
 277 port_in_ah_lb(64, 1, 1, 1)
 278
 279 static rte_pipeline_port_in_action_handler
 280 get_port_in_ah(struct pipeline_passthrough *p)
 281 {
 282         if (p->params.dma_enabled == 0)
 283                 return NULL;
 284
 285         if (p->params.dma_hash_enabled) {
 286                 if (p->params.lb_hash_enabled) {
 287                         if (rte_is_power_of_2(p->p.n_ports_out))
 288                                 switch (p->params.dma_size) {
 289
 290                                 case 8: return port_in_ah_size8_hash1_lb1_pw1;
 291                                 case 16: return port_in_ah_size16_hash1_lb1_pw1;
 292                                 case 24: return port_in_ah_size24_hash1_lb1_pw1;
 293                                 case 32: return port_in_ah_size32_hash1_lb1_pw1;
 294                                 case 40: return port_in_ah_size40_hash1_lb1_pw1;
 295                                 case 48: return port_in_ah_size48_hash1_lb1_pw1;
 296                                 case 56: return port_in_ah_size56_hash1_lb1_pw1;
 297                                 case 64: return port_in_ah_size64_hash1_lb1_pw1;
 298                                 default: return NULL;
 299                                 }
 300                         else
 301                                 switch (p->params.dma_size) {
 302
 303                                 case 8: return port_in_ah_size8_hash1_lb1_pw0;
 304                                 case 16: return port_in_ah_size16_hash1_lb1_pw0;
 305                                 case 24: return port_in_ah_size24_hash1_lb1_pw0;
 306                                 case 32: return port_in_ah_size32_hash1_lb1_pw0;
 307                                 case 40: return port_in_ah_size40_hash1_lb1_pw0;
 308                                 case 48: return port_in_ah_size48_hash1_lb1_pw0;
 309                                 case 56: return port_in_ah_size56_hash1_lb1_pw0;
 310                                 case 64: return port_in_ah_size64_hash1_lb1_pw0;
 311                                 default: return NULL;
 312                         }
 313                 } else
 314                         switch (p->params.dma_size) {
 315
 316                         case 8: return port_in_ah_size8_hash1_lb0_pw0;
 317                         case 16: return port_in_ah_size16_hash1_lb0_pw0;
 318                         case 24: return port_in_ah_size24_hash1_lb0_pw0;
 319                         case 32: return port_in_ah_size32_hash1_lb0_pw0;
 320                         case 40: return port_in_ah_size40_hash1_lb0_pw0;
 321                         case 48: return port_in_ah_size48_hash1_lb0_pw0;
 322                         case 56: return port_in_ah_size56_hash1_lb0_pw0;
 323                         case 64: return port_in_ah_size64_hash1_lb0_pw0;
 324                         default: return NULL;
 325                 }
 326         } else
 327                 switch (p->params.dma_size) {
 328
 329                 case 8: return port_in_ah_size8_hash0_lb0_pw0;
 330                 case 16: return port_in_ah_size16_hash0_lb0_pw0;
 331                 case 24: return port_in_ah_size24_hash0_lb0_pw0;
 332                 case 32: return port_in_ah_size32_hash0_lb0_pw0;
 333                 case 40: return port_in_ah_size40_hash0_lb0_pw0;
 334                 case 48: return port_in_ah_size48_hash0_lb0_pw0;
 335                 case 56: return port_in_ah_size56_hash0_lb0_pw0;
 336                 case 64: return port_in_ah_size64_hash0_lb0_pw0;
 337                 default: return NULL;
 338                 }
 339 }
 340
 341 int
 342 pipeline_passthrough_parse_args(struct pipeline_passthrough_params *p,
 343         struct pipeline_params *params)
 344 {
 345         uint32_t dma_dst_offset_present = 0;
 346         uint32_t dma_src_offset_present = 0;
 347         uint32_t dma_src_mask_present = 0;
 348         uint32_t dma_size_present = 0;
 349         uint32_t dma_hash_offset_present = 0;
 350         uint32_t lb_present = 0;
 351         uint32_t i;
 352         char dma_mask_str[PIPELINE_PASSTHROUGH_DMA_SIZE_MAX * 2];
 353
 354         /* default values */
 355         p->dma_enabled = 0;
 356         p->dma_hash_enabled = 0;
 357         p->lb_hash_enabled = 0;
 358         memset(p->dma_src_mask, 0xFF, sizeof(p->dma_src_mask));
 359
 360         for (i = 0; i < params->n_args; i++) {
 361                 char *arg_name = params->args_name[i];
 362                 char *arg_value = params->args_value[i];
 363
 364                 /* dma_dst_offset */
 365                 if (strcmp(arg_name, "dma_dst_offset") == 0) {
 366                         int status;
 367
 368                         PIPELINE_PARSE_ERR_DUPLICATE(
 369                                 dma_dst_offset_present == 0, params->name,
 370                                 arg_name);
 371                         dma_dst_offset_present = 1;
 372
 373                         status = parser_read_uint32(&p->dma_dst_offset,
 374                                 arg_value);
 375                         PIPELINE_PARSE_ERR_INV_VAL((status != -EINVAL),
 376                                 params->name, arg_name, arg_value);
 377                         PIPELINE_PARSE_ERR_OUT_RNG((status != -ERANGE),
 378                                 params->name, arg_name, arg_value);
 379
 380                         p->dma_enabled = 1;
 381
 382                         continue;
 383                 }
 384
 385                 /* dma_src_offset */
 386                 if (strcmp(arg_name, "dma_src_offset") == 0) {
 387                         int status;
 388
 389                         PIPELINE_PARSE_ERR_DUPLICATE(
 390                                 dma_src_offset_present == 0, params->name,
 391                                 arg_name);
 392                         dma_src_offset_present = 1;
 393
 394                         status = parser_read_uint32(&p->dma_src_offset,
 395                                 arg_value);
 396                         PIPELINE_PARSE_ERR_INV_VAL((status != -EINVAL),
 397                                 params->name, arg_name, arg_value);
 398                         PIPELINE_PARSE_ERR_OUT_RNG((status != -ERANGE),
 399                                 params->name, arg_name, arg_value);
 400
 401                         p->dma_enabled = 1;
 402
 403                         continue;
 404                 }
 405
 406                 /* dma_size */
 407                 if (strcmp(arg_name, "dma_size") == 0) {
 408                         int status;
 409
 410                         PIPELINE_PARSE_ERR_DUPLICATE(
 411                                 dma_size_present == 0, params->name,
 412                                 arg_name);
 413                         dma_size_present = 1;
 414
 415                         status = parser_read_uint32(&p->dma_size,
 416                                 arg_value);
 417                         PIPELINE_PARSE_ERR_INV_VAL(((status != -EINVAL) &&
 418                                 (p->dma_size != 0) &&
 419                                 ((p->dma_size % 8) == 0)),
 420                                 params->name, arg_name, arg_value);
 421                         PIPELINE_PARSE_ERR_OUT_RNG(((status != -ERANGE) &&
 422                                 (p->dma_size <=
 423                                 PIPELINE_PASSTHROUGH_DMA_SIZE_MAX)),
 424                                 params->name, arg_name, arg_value);
 425
 426                         p->dma_enabled = 1;
 427
 428                         continue;
 429                 }
 430
 431                 /* dma_src_mask */
 432                 if (strcmp(arg_name, "dma_src_mask") == 0) {
 433                         int mask_str_len = strlen(arg_value);
 434
 435                         PIPELINE_PARSE_ERR_DUPLICATE(
 436                                 dma_src_mask_present == 0,
 437                                 params->name, arg_name);
 438                         dma_src_mask_present = 1;
 439
 440                         PIPELINE_ARG_CHECK((mask_str_len <
 441                                 (PIPELINE_PASSTHROUGH_DMA_SIZE_MAX * 2)),
 442                                 "Parse error in section \"%s\": entry "
 443                                 "\"%s\" too long", params->name,
 444                                 arg_name);
 445
 446                         snprintf(dma_mask_str, mask_str_len + 1,
 447                                 "%s", arg_value);
 448
 449                         p->dma_enabled = 1;
 450
 451                         continue;
 452                 }
 453
 454                 /* dma_hash_offset */
 455                 if (strcmp(arg_name, "dma_hash_offset") == 0) {
 456                         int status;
 457
 458                         PIPELINE_PARSE_ERR_DUPLICATE(
 459                                 dma_hash_offset_present == 0,
 460                                 params->name, arg_name);
 461                         dma_hash_offset_present = 1;
 462
 463                         status = parser_read_uint32(&p->dma_hash_offset,
 464                                 arg_value);
 465                         PIPELINE_PARSE_ERR_INV_VAL((status != -EINVAL),
 466                                 params->name, arg_name, arg_value);
 467                         PIPELINE_PARSE_ERR_OUT_RNG((status != -ERANGE),
 468                                 params->name, arg_name, arg_value);
 469
 470                         p->dma_hash_enabled = 1;
 471                         p->dma_enabled = 1;
 472
 473                         continue;
 474                 }
 475
 476                 /* load_balance mode */
 477                 if (strcmp(arg_name, "lb") == 0) {
 478                         PIPELINE_PARSE_ERR_DUPLICATE(
 479                                 lb_present == 0,
 480                                 params->name, arg_name);
 481                         lb_present = 1;
 482
 483                         if ((strcmp(arg_value, "hash") == 0) ||
 484                                 (strcmp(arg_value, "HASH") == 0))
 485                                 p->lb_hash_enabled = 1;
 486                         else
 487                                 PIPELINE_PARSE_ERR_INV_VAL(0,
 488                                         params->name,
 489                                         arg_name,
 490                                         arg_value);
 491
 492                         continue;
 493                 }
 494
 495                 /* any other */
 496                 PIPELINE_PARSE_ERR_INV_ENT(0, params->name, arg_name);
 497         }
 498
 499         /* Check correlations between arguments */
 500         PIPELINE_ARG_CHECK((dma_dst_offset_present == p->dma_enabled),
 501                 "Parse error in section \"%s\": missing entry "
 502                 "\"dma_dst_offset\"", params->name);
 503         PIPELINE_ARG_CHECK((dma_src_offset_present == p->dma_enabled),
 504                 "Parse error in section \"%s\": missing entry "
 505                 "\"dma_src_offset\"", params->name);
 506         PIPELINE_ARG_CHECK((dma_size_present == p->dma_enabled),
 507                 "Parse error in section \"%s\": missing entry "
 508                 "\"dma_size\"", params->name);
 509         PIPELINE_ARG_CHECK((dma_hash_offset_present == p->dma_enabled),
 510                 "Parse error in section \"%s\": missing entry "
 511                 "\"dma_hash_offset\"", params->name);
 512         PIPELINE_ARG_CHECK((p->lb_hash_enabled <= p->dma_hash_enabled),
 513                 "Parse error in section \"%s\": missing entry "
 514                 "\"dma_hash_offset\"", params->name);
 515
 516         if (dma_src_mask_present) {
 517                 uint32_t dma_size = p->dma_size;
 518                 int status;
 519
 520                 PIPELINE_ARG_CHECK((strlen(dma_mask_str) ==
 521                         (dma_size * 2)), "Parse error in section "
 522                         "\"%s\": dma_src_mask should have exactly %u hex "
 523                         "digits", params->name, (dma_size * 2));
 524
 525                 status = parse_hex_string(dma_mask_str, p->dma_src_mask,
 526                         &p->dma_size);
 527
 528                 PIPELINE_PARSE_ERR_INV_VAL(((status == 0) &&
 529                         (dma_size == p->dma_size)), params->name,
 530                         "dma_src_mask", dma_mask_str);
 531         }
 532
 533         return 0;
 534 }
 535
 536
 537 static rte_table_hash_op_hash
 538 get_hash_function(struct pipeline_passthrough *p)
 539 {
 540         switch (p->params.dma_size) {
 541
 542         case 8: return hash_default_key8;
 543         case 16: return hash_default_key16;
 544         case 24: return hash_default_key24;
 545         case 32: return hash_default_key32;
 546         case 40: return hash_default_key40;
 547         case 48: return hash_default_key48;
 548         case 56: return hash_default_key56;
 549         case 64: return hash_default_key64;
 550         default: return NULL;
 551         }
 552 }
 553
 554 static void*
 555 pipeline_passthrough_init(struct pipeline_params *params,
 556         __rte_unused void *arg)
 557 {
 558         struct pipeline *p;
 559         struct pipeline_passthrough *p_pt;
 560         uint32_t size, i;
 561
 562         /* Check input arguments */
 563         if ((params == NULL) ||
 564                 (params->n_ports_in == 0) ||
 565                 (params->n_ports_out == 0) ||
 566                 (params->n_ports_in < params->n_ports_out) ||
 567                 (params->n_ports_in % params->n_ports_out))
 568                 return NULL;
 569
 570         /* Memory allocation */
 571         size = RTE_CACHE_LINE_ROUNDUP(sizeof(struct pipeline_passthrough));
 572         p = rte_zmalloc(NULL, size, RTE_CACHE_LINE_SIZE);
 573         p_pt = (struct pipeline_passthrough *) p;
 574         if (p == NULL)
 575                 return NULL;
 576
 577         strcpy(p->name, params->name);
 578         p->log_level = params->log_level;
 579
 580         PLOG(p, HIGH, "Pass-through");
 581
 582         /* Parse arguments */
 583         if (pipeline_passthrough_parse_args(&p_pt->params, params))
 584                 return NULL;
 585         p_pt->f_hash = get_hash_function(p_pt);
 586
 587         /* Pipeline */
 588         {
 589                 struct rte_pipeline_params pipeline_params = {
 590                         .name = "PASS-THROUGH",
 591                         .socket_id = params->socket_id,
 592                         .offset_port_id = 0,
 593                 };
 594
 595                 p->p = rte_pipeline_create(&pipeline_params);
 596                 if (p->p == NULL) {
 597                         rte_free(p);
 598                         return NULL;
 599                 }
 600         }
 601
 602         p->n_ports_in = params->n_ports_in;
 603         p->n_ports_out = params->n_ports_out;
 604         p->n_tables = p->n_ports_in;
 605
 606         /*Input ports*/
 607         for (i = 0; i < p->n_ports_in; i++) {
 608                 struct rte_pipeline_port_in_params port_params = {
 609                         .ops = pipeline_port_in_params_get_ops(
 610                                 &params->port_in[i]),
 611                         .arg_create = pipeline_port_in_params_convert(
 612                                 &params->port_in[i]),
 613                         .f_action = get_port_in_ah(p_pt),
 614                         .arg_ah = p_pt,
 615                         .burst_size = params->port_in[i].burst_size,
 616                 };
 617
 618                 int status = rte_pipeline_port_in_create(p->p,
 619                         &port_params,
 620                         &p->port_in_id[i]);
 621
 622                 if (status) {
 623                         rte_pipeline_free(p->p);
 624                         rte_free(p);
 625                         return NULL;
 626                 }
 627         }
 628
 629         /* Output ports */
 630         for (i = 0; i < p->n_ports_out; i++) {
 631                 struct rte_pipeline_port_out_params port_params = {
 632                         .ops = pipeline_port_out_params_get_ops(
 633                                 &params->port_out[i]),
 634                         .arg_create = pipeline_port_out_params_convert(
 635                                 &params->port_out[i]),
 636                         .f_action = NULL,
 637                         .arg_ah = NULL,
 638                 };
 639
 640                 int status = rte_pipeline_port_out_create(p->p,
 641                         &port_params,
 642                         &p->port_out_id[i]);
 643
 644                 if (status) {
 645                         rte_pipeline_free(p->p);
 646                         rte_free(p);
 647                         return NULL;
 648                 }
 649         }
 650
 651         /* Tables */
 652         for (i = 0; i < p->n_ports_in; i++) {
 653                 struct rte_pipeline_table_params table_params = {
 654                         .ops = &rte_table_stub_ops,
 655                         .arg_create = NULL,
 656                         .f_action_hit = NULL,
 657                         .f_action_miss = NULL,
 658                         .arg_ah = NULL,
 659                         .action_data_size = 0,
 660                 };
 661
 662                 int status = rte_pipeline_table_create(p->p,
 663                         &table_params,
 664                         &p->table_id[i]);
 665
 666                 if (status) {
 667                         rte_pipeline_free(p->p);
 668                         rte_free(p);
 669                         return NULL;
 670                 }
 671         }
 672
 673         /* Connecting input ports to tables */
 674         for (i = 0; i < p->n_ports_in; i++) {
 675                 int status = rte_pipeline_port_in_connect_to_table(p->p,
 676                         p->port_in_id[i],
 677                         p->table_id[i]);
 678
 679                 if (status) {
 680                         rte_pipeline_free(p->p);
 681                         rte_free(p);
 682                         return NULL;
 683                 }
 684         }
 685
 686         /* Add entries to tables */
 687         for (i = 0; i < p->n_ports_in; i++) {
 688                 struct rte_pipeline_table_entry default_entry = {
 689                         .action = RTE_PIPELINE_ACTION_PORT,
 690                         {.port_id = p->port_out_id[
 691                                 i / (p->n_ports_in / p->n_ports_out)]},
 692                 };
 693
 694                 struct rte_pipeline_table_entry *default_entry_ptr;
 695
 696                 int status = rte_pipeline_table_default_entry_add(p->p,
 697                         p->table_id[i],
 698                         &default_entry,
 699                         &default_entry_ptr);
 700
 701                 if (status) {
 702                         rte_pipeline_free(p->p);
 703                         rte_free(p);
 704                         return NULL;
 705                 }
 706         }
 707
 708         /* Enable input ports */
 709         for (i = 0; i < p->n_ports_in; i++) {
 710                 int status = rte_pipeline_port_in_enable(p->p,
 711                         p->port_in_id[i]);
 712
 713                 if (status) {
 714                         rte_pipeline_free(p->p);
 715                         rte_free(p);
 716                         return NULL;
 717                 }
 718         }
 719
 720         /* Check pipeline consistency */
 721         if (rte_pipeline_check(p->p) < 0) {
 722                 rte_pipeline_free(p->p);
 723                 rte_free(p);
 724                 return NULL;
 725         }
 726
 727         /* Message queues */
 728         p->n_msgq = params->n_msgq;
 729         for (i = 0; i < p->n_msgq; i++)
 730                 p->msgq_in[i] = params->msgq_in[i];
 731         for (i = 0; i < p->n_msgq; i++)
 732                 p->msgq_out[i] = params->msgq_out[i];
 733
 734         /* Message handlers */
 735         memcpy(p->handlers, handlers, sizeof(p->handlers));
 736
 737         return p;
 738 }
 739
 740 static int
 741 pipeline_passthrough_free(void *pipeline)
 742 {
 743         struct pipeline *p = (struct pipeline *) pipeline;
 744
 745         /* Check input arguments */
 746         if (p == NULL)
 747                 return -1;
 748
 749         /* Free resources */
 750         rte_pipeline_free(p->p);
 751         rte_free(p);
 752         return 0;
 753 }
 754
 755 static int
 756 pipeline_passthrough_timer(void *pipeline)
 757 {
 758         struct pipeline *p = (struct pipeline *) pipeline;
 759
 760         pipeline_msg_req_handle(p);
 761         rte_pipeline_flush(p->p);
 762
 763         return 0;
 764 }
 765
 766 static int
 767 pipeline_passthrough_track(void *pipeline, uint32_t port_in, uint32_t *port_out)
 768 {
 769         struct pipeline *p = (struct pipeline *) pipeline;
 770
 771         /* Check input arguments */
 772         if ((p == NULL) ||
 773                 (port_in >= p->n_ports_in) ||
 774                 (port_out == NULL))
 775                 return -1;
 776
 777         *port_out = port_in / p->n_ports_in;
 778         return 0;
 779 }
 780
 781 struct pipeline_be_ops pipeline_passthrough_be_ops = {
 782         .f_init = pipeline_passthrough_init,
 783         .f_free = pipeline_passthrough_free,
 784         .f_run = NULL,
 785         .f_timer = pipeline_passthrough_timer,
 786         .f_track = pipeline_passthrough_track,
 787 };