2 // Copyright (c) 2017 Intel Corporation
4 // Licensed under the Apache License, Version 2.0 (the "License");
5 // you may not use this file except in compliance with the License.
6 // You may obtain a copy of the License at
8 // http://www.apache.org/licenses/LICENSE-2.0
10 // Unless required by applicable law or agreed to in writing, software
11 // distributed under the License is distributed on an "AS IS" BASIS,
12 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 // See the License for the specific language governing permissions and
14 // limitations under the License.
17 #include <immintrin.h>
22 #include "rte_atomic.h"
27 run_cpuid (uint32_t eax, uint32_t ecx, uint32_t *abcd)
29 uint32_t ebx = 0, edx = 0;
31 #if defined(__i386__) && defined (__PIC__)
32 /* in case of PIC under 32-bit EBX cannot be clobbered */
33 __asm__ ("movl %%ebx, %%edi \n\t cpuid \n\t xchgl %%ebx, %%edi":"=D" (ebx),
35 __asm__ ("cpuid":"+b" (ebx),
37 "+a" (eax), "+c" (ecx), "=d" (edx));
48 __asm__ ("xgetbv" : "=a" (xcr0) : "c" (0) : "%edx");
49 return ((xcr0 & 6) == 6);/* checking if xmm and ymm state are enabled in XCR0 */
53 check_4th_gen_intel_core_features (void)
56 uint32_t fma_movbe_osxsave_mask = ((1 << 12) | (1 << 22) | (1 << 27));
57 uint32_t avx2_bmi12_mask = (1 << 5) | (1 << 3) | (1 << 8);
59 /* CPUID.(EAX=01H, ECX=0H):ECX.FMA[bit 12]==1 &&
60 CPUID.(EAX=01H, ECX=0H):ECX.MOVBE[bit 22]==1 &&
61 CPUID.(EAX=01H, ECX=0H):ECX.OSXSAVE[bit 27]==1 */
62 run_cpuid (1, 0, abcd);
63 if ((abcd[2] & fma_movbe_osxsave_mask) != fma_movbe_osxsave_mask) {
64 printf ("Failing in if cond-1\n");
67 if (!check_xcr0_ymm ()) {
68 printf ("Failing in if cond-2\n");
72 /* CPUID.(EAX=07H, ECX=0H):EBX.AVX2[bit 5]==1 &&
73 CPUID.(EAX=07H, ECX=0H):EBX.BMI1[bit 3]==1 &&
74 CPUID.(EAX=07H, ECX=0H):EBX.BMI2[bit 8]==1 */
75 run_cpuid (7, 0, abcd);
76 if ((abcd[1] & avx2_bmi12_mask) != avx2_bmi12_mask) {
77 printf ("Failing in if cond-3\n");
80 /* CPUID.(EAX=80000001H):ECX.LZCNT[bit 5]==1 */
81 run_cpuid (0x80000001, 0, abcd);
82 if ((abcd[2] & (1 << 5)) == 0) {
83 printf ("Failing in if cond-4\n");
86 /* CPUID.(EAX=07H, ECX=0H).EBX.RTM[bit 11]==1 */
87 run_cpuid (7, 0, abcd);
88 if ((abcd[1] & (1 << 11)) == 0) {
89 printf ("Failing in if cond-5\n");
92 /* CPUID.(EAX=07H, ECX=0H).EBX.HLE[bit 4]==1 */
93 run_cpuid (7, 0, abcd);
94 if ((abcd[1] & (1 << 4)) == 0) {
95 printf ("Failing in if cond-6\n");
102 can_use_intel_core_4th_gen_features (void)
104 static int the_4th_gen_features_available = -1;
105 /* test is performed once */
106 if (the_4th_gen_features_available < 0)
107 the_4th_gen_features_available = check_4th_gen_intel_core_features ();
108 return the_4th_gen_features_available;
114 naborted = (rte_atomic64_t) RTE_ATOMIC64_INIT (0);
116 //RTE_ATOMIC64_INIT(naborted);
124 unsigned int status = _xbegin ();
125 if (status == _XBEGIN_STARTED) {
126 if (!is_hle_locked ())
127 return 1; // successfully started transaction
128 // started transaction but someone executes the transaction section
129 // non-speculatively (acquired the fall-back lock)
130 _xabort (0xff); // abort with code 0xff
133 rte_atomic64_inc (&naborted); // do abort statistics
135 ("DEBUG: Transaction aborted: %d time(s) with the status: %u\n",
137 // handle _xabort(0xff) from above
138 if ((status & _XABORT_EXPLICIT)
139 && _XABORT_CODE (status) == 0xff && !(status & _XABORT_NESTED)) {
140 while (is_hle_locked ())
141 _mm_pause (); // wait until lock is free
143 else if (!(status & _XABORT_RETRY))
144 break; // take the fall-back lock if the retry abort flag is not set
145 if (nretries >= max_retries)
146 break; // too many retries, take the fall-back lock
155 if (is_hle_locked ())
166 return ((int) _xtest ());