2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
5 * Original from Linux kernel 3.0.1
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23 #include "ar9002_phy.h"
25 static void ath9k_get_txgain_index(struct ath_hw *ah,
26 struct ath9k_channel *chan,
27 struct calDataPerFreqOpLoop *rawDatasetOpLoop,
28 u8 *calChans, u16 availPiers, u8 *pwr, u8 *pcdacIdx)
31 u16 idxL = 0, idxR = 0, numPiers;
33 struct chan_centers centers;
35 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
37 for (numPiers = 0; numPiers < availPiers; numPiers++)
38 if (calChans[numPiers] == AR5416_BCHAN_UNUSED)
41 match = ath9k_hw_get_lower_upper_index(
42 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
43 calChans, numPiers, &idxL, &idxR);
45 pcdac = rawDatasetOpLoop[idxL].pcdac[0][0];
46 *pwr = rawDatasetOpLoop[idxL].pwrPdg[0][0];
48 pcdac = rawDatasetOpLoop[idxR].pcdac[0][0];
49 *pwr = (rawDatasetOpLoop[idxL].pwrPdg[0][0] +
50 rawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
53 while (pcdac > ah->originalGain[i] &&
54 i < (AR9280_TX_GAIN_TABLE_SIZE - 1))
60 static void ath9k_olc_get_pdadcs(struct ath_hw *ah,
68 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0,
69 AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
70 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1,
71 AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
73 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7,
74 AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, initTxGain);
77 for (i = 0; i < AR5416_NUM_PDADC_VALUES; i++)
79 pPDADCValues[i] = 0x0;
81 pPDADCValues[i] = 0xFF;
84 static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah)
86 return ((ah->eeprom.def.baseEepHeader.version >> 12) & 0xF);
89 static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah)
91 return ((ah->eeprom.def.baseEepHeader.version) & 0xFFF);
94 #define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
96 static int __ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
98 struct ath_common *common = ath9k_hw_common(ah);
99 u16 *eep_data = (u16 *)&ah->eeprom.def;
101 int ar5416_eep_start_loc = 0x100;
103 for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
104 if (!ath9k_hw_nvram_read(common, addr + ar5416_eep_start_loc,
107 "Unable to read eeprom region\n");
115 static int __ath9k_hw_usb_def_fill_eeprom(struct ath_hw *ah)
117 u16 *eep_data = (u16 *)&ah->eeprom.def;
119 ath9k_hw_usb_gen_fill_eeprom(ah, eep_data,
120 0x100, SIZE_EEPROM_DEF);
124 static int ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
126 struct ath_common *common = ath9k_hw_common(ah);
128 if (!ath9k_hw_use_flash(ah)) {
130 "Reading from EEPROM, not flash\n");
133 if (common->bus_ops->ath_bus_type == ATH_USB)
134 return __ath9k_hw_usb_def_fill_eeprom(ah);
136 return __ath9k_hw_def_fill_eeprom(ah);
139 #undef SIZE_EEPROM_DEF
141 static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
143 struct ar5416_eeprom_def *eep =
144 (struct ar5416_eeprom_def *) &ah->eeprom.def;
145 struct ath_common *common = ath9k_hw_common(ah);
146 u16 *eepdata, temp, magic, magic2;
149 unsigned int i, addr, size;
151 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
152 DBG("ath9k: Reading Magic # failed\n");
156 if (!ath9k_hw_use_flash(ah)) {
158 "Read Magic = 0x%04X\n", magic);
160 if (magic != AR5416_EEPROM_MAGIC) {
161 magic2 = swab16(magic);
163 if (magic2 == AR5416_EEPROM_MAGIC) {
164 size = sizeof(struct ar5416_eeprom_def);
166 eepdata = (u16 *) (&ah->eeprom);
168 for (addr = 0; addr < size / sizeof(u16); addr++) {
169 temp = swab16(*eepdata);
175 "Invalid EEPROM Magic. Endianness mismatch.\n");
181 DBG2("ath9k: need_swap = %s.\n",
182 need_swap ? "True" : "False");
185 el = swab16(ah->eeprom.def.baseEepHeader.length);
187 el = ah->eeprom.def.baseEepHeader.length;
189 if (el > sizeof(struct ar5416_eeprom_def))
190 el = sizeof(struct ar5416_eeprom_def) / sizeof(u16);
192 el = el / sizeof(u16);
194 eepdata = (u16 *)(&ah->eeprom);
196 for (i = 0; i < el; i++)
204 "EEPROM Endianness is not native.. Changing.\n");
206 word = swab16(eep->baseEepHeader.length);
207 eep->baseEepHeader.length = word;
209 word = swab16(eep->baseEepHeader.checksum);
210 eep->baseEepHeader.checksum = word;
212 word = swab16(eep->baseEepHeader.version);
213 eep->baseEepHeader.version = word;
215 word = swab16(eep->baseEepHeader.regDmn[0]);
216 eep->baseEepHeader.regDmn[0] = word;
218 word = swab16(eep->baseEepHeader.regDmn[1]);
219 eep->baseEepHeader.regDmn[1] = word;
221 word = swab16(eep->baseEepHeader.rfSilent);
222 eep->baseEepHeader.rfSilent = word;
224 word = swab16(eep->baseEepHeader.blueToothOptions);
225 eep->baseEepHeader.blueToothOptions = word;
227 word = swab16(eep->baseEepHeader.deviceCap);
228 eep->baseEepHeader.deviceCap = word;
230 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
231 struct modal_eep_header *pModal =
232 &eep->modalHeader[j];
233 integer = swab32(pModal->antCtrlCommon);
234 pModal->antCtrlCommon = integer;
236 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
237 integer = swab32(pModal->antCtrlChain[i]);
238 pModal->antCtrlChain[i] = integer;
240 for (i = 0; i < 3; i++) {
241 word = swab16(pModal->xpaBiasLvlFreq[i]);
242 pModal->xpaBiasLvlFreq[i] = word;
245 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
246 word = swab16(pModal->spurChans[i].spurChan);
247 pModal->spurChans[i].spurChan = word;
252 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
253 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
254 DBG("ath9k: Bad EEPROM checksum 0x%x or revision 0x%04x\n",
255 sum, ah->eep_ops->get_eeprom_ver(ah));
259 /* Enable fixup for AR_AN_TOP2 if necessary */
260 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
261 ((eep->baseEepHeader.version & 0xff) > 0x0a) &&
262 (eep->baseEepHeader.pwdclkind == 0))
263 ah->need_an_top2_fixup = 1;
265 if ((common->bus_ops->ath_bus_type == ATH_USB) &&
267 eep->modalHeader[0].xpaBiasLvl = 0;
272 static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
273 enum eeprom_param param)
275 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
276 struct modal_eep_header *pModal = eep->modalHeader;
277 struct base_eep_header *pBase = &eep->baseEepHeader;
281 return pModal[0].noiseFloorThreshCh[0];
283 return pModal[1].noiseFloorThreshCh[0];
285 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
287 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
289 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
291 return pBase->regDmn[0];
293 return pBase->regDmn[1];
295 return pBase->deviceCap;
297 return pBase->opCapFlags;
299 return pBase->rfSilent;
309 return AR5416_VER_MASK;
311 return pBase->txMask;
313 return pBase->rxMask;
315 return pBase->fastClk5g;
316 case EEP_RXGAIN_TYPE:
317 return pBase->rxGainType;
318 case EEP_TXGAIN_TYPE:
319 return pBase->txGainType;
321 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
322 return pBase->openLoopPwrCntl ? 1 : 0;
325 case EEP_RC_CHAIN_MASK:
326 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
327 return pBase->rcChainMask;
330 case EEP_DAC_HPWR_5G:
331 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20)
332 return pBase->dacHiPwrMode_5G;
336 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_22)
337 return pBase->frac_n_5g;
340 case EEP_PWR_TABLE_OFFSET:
341 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_21)
342 return pBase->pwr_table_offset;
344 return AR5416_PWR_TABLE_OFFSET_DB;
350 static void ath9k_hw_def_set_gain(struct ath_hw *ah,
351 struct modal_eep_header *pModal,
352 struct ar5416_eeprom_def *eep,
353 u8 txRxAttenLocal, int regChainOffset, int i)
355 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
356 txRxAttenLocal = pModal->txRxAttenCh[i];
358 if (AR_SREV_9280_20_OR_LATER(ah)) {
359 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
360 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
361 pModal->bswMargin[i]);
362 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
363 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
364 pModal->bswAtten[i]);
365 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
366 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
367 pModal->xatten2Margin[i]);
368 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
369 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
370 pModal->xatten2Db[i]);
372 REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
373 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
374 ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
375 | SM(pModal-> bswMargin[i],
376 AR_PHY_GAIN_2GHZ_BSW_MARGIN));
377 REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
378 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
379 ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
380 | SM(pModal->bswAtten[i],
381 AR_PHY_GAIN_2GHZ_BSW_ATTEN));
385 if (AR_SREV_9280_20_OR_LATER(ah)) {
387 AR_PHY_RXGAIN + regChainOffset,
388 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
390 AR_PHY_RXGAIN + regChainOffset,
391 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]);
394 AR_PHY_RXGAIN + regChainOffset,
395 (REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) &
396 ~AR_PHY_RXGAIN_TXRX_ATTEN)
397 | SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN));
399 AR_PHY_GAIN_2GHZ + regChainOffset,
400 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
401 ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
402 SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
406 static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
407 struct ath9k_channel *chan)
409 struct modal_eep_header *pModal;
410 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
411 int i, regChainOffset;
414 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
415 txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
417 REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon & 0xffff);
419 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
420 if (AR_SREV_9280(ah)) {
425 if (AR_SREV_5416_20_OR_LATER(ah) &&
426 (ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0))
427 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
429 regChainOffset = i * 0x1000;
431 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
432 pModal->antCtrlChain[i]);
434 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
435 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
436 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
437 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
438 SM(pModal->iqCalICh[i],
439 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
440 SM(pModal->iqCalQCh[i],
441 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
443 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah))
444 ath9k_hw_def_set_gain(ah, pModal, eep, txRxAttenLocal,
448 if (AR_SREV_9280_20_OR_LATER(ah)) {
449 if (IS_CHAN_2GHZ(chan)) {
450 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
452 AR_AN_RF2G1_CH0_OB_S,
454 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
456 AR_AN_RF2G1_CH0_DB_S,
458 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
460 AR_AN_RF2G1_CH1_OB_S,
462 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
464 AR_AN_RF2G1_CH1_DB_S,
467 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
469 AR_AN_RF5G1_CH0_OB5_S,
471 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
473 AR_AN_RF5G1_CH0_DB5_S,
475 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
477 AR_AN_RF5G1_CH1_OB5_S,
479 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
481 AR_AN_RF5G1_CH1_DB5_S,
484 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
485 AR_AN_TOP2_XPABIAS_LVL,
486 AR_AN_TOP2_XPABIAS_LVL_S,
488 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
489 AR_AN_TOP2_LOCALBIAS,
490 AR_AN_TOP2_LOCALBIAS_S,
492 LNA_CTL_LOCAL_BIAS));
493 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
494 !!(pModal->lna_ctl & LNA_CTL_FORCE_XPA));
497 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
498 pModal->switchSettling);
499 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
500 pModal->adcDesiredSize);
502 if (!AR_SREV_9280_20_OR_LATER(ah))
503 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
504 AR_PHY_DESIRED_SZ_PGA,
505 pModal->pgaDesiredSize);
507 REG_WRITE(ah, AR_PHY_RF_CTL4,
508 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
509 | SM(pModal->txEndToXpaOff,
510 AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
511 | SM(pModal->txFrameToXpaOn,
512 AR_PHY_RF_CTL4_FRAME_XPAA_ON)
513 | SM(pModal->txFrameToXpaOn,
514 AR_PHY_RF_CTL4_FRAME_XPAB_ON));
516 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
517 pModal->txEndToRxOn);
519 if (AR_SREV_9280_20_OR_LATER(ah)) {
520 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
522 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
523 AR_PHY_EXT_CCA0_THRESH62,
526 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
528 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
529 AR_PHY_EXT_CCA_THRESH62,
533 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) {
534 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
535 AR_PHY_TX_END_DATA_START,
536 pModal->txFrameToDataStart);
537 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
538 pModal->txFrameToPaOn);
541 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
542 if (IS_CHAN_HT40(chan))
543 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
544 AR_PHY_SETTLING_SWITCH,
545 pModal->swSettleHt40);
548 if (AR_SREV_9280_20_OR_LATER(ah) &&
549 AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
550 REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL,
551 AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
555 if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) {
556 if (IS_CHAN_2GHZ(chan))
557 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
558 eep->baseEepHeader.dacLpMode);
559 else if (eep->baseEepHeader.dacHiPwrMode_5G)
560 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0);
562 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
563 eep->baseEepHeader.dacLpMode);
567 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP,
568 pModal->miscBits >> 2);
570 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9,
571 AR_PHY_TX_DESIRED_SCALE_CCK,
572 eep->baseEepHeader.desiredScaleCCK);
576 static void ath9k_hw_def_set_addac(struct ath_hw *ah,
577 struct ath9k_channel *chan)
579 #define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt])
580 struct modal_eep_header *pModal;
581 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
584 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
587 if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
590 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
592 if (pModal->xpaBiasLvl != 0xff) {
593 biaslevel = pModal->xpaBiasLvl;
595 u16 resetFreqBin, freqBin, freqCount = 0;
596 struct chan_centers centers;
598 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
600 resetFreqBin = FREQ2FBIN(centers.synth_center,
602 freqBin = XPA_LVL_FREQ(0) & 0xff;
603 biaslevel = (u8) (XPA_LVL_FREQ(0) >> 14);
607 while (freqCount < 3) {
608 if (XPA_LVL_FREQ(freqCount) == 0x0)
611 freqBin = XPA_LVL_FREQ(freqCount) & 0xff;
612 if (resetFreqBin >= freqBin)
613 biaslevel = (u8)(XPA_LVL_FREQ(freqCount) >> 14);
620 if (IS_CHAN_2GHZ(chan)) {
621 INI_RA(&ah->iniAddac, 7, 1) = (INI_RA(&ah->iniAddac,
622 7, 1) & (~0x18)) | biaslevel << 3;
624 INI_RA(&ah->iniAddac, 6, 1) = (INI_RA(&ah->iniAddac,
625 6, 1) & (~0xc0)) | biaslevel << 6;
630 static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah,
633 u16 pdGainOverlap_t2,
634 int8_t pwr_table_offset,
640 /* Prior to writing the boundaries or the pdadc vs. power table
641 * into the chip registers the default starting point on the pdadc
642 * vs. power table needs to be checked and the curve boundaries
643 * adjusted accordingly
645 if (AR_SREV_9280_20_OR_LATER(ah)) {
648 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
649 /* get the difference in dB */
650 *diff = (u16)(pwr_table_offset - AR5416_PWR_TABLE_OFFSET_DB);
651 /* get the number of half dB steps */
653 /* change the original gain boundary settings
654 * by the number of half dB steps
656 for (k = 0; k < numXpdGain; k++)
657 gb[k] = (u16)(gb[k] - *diff);
659 /* Because of a hardware limitation, ensure the gain boundary
660 * is not larger than (63 - overlap)
662 gb_limit = (u16)(MAX_RATE_POWER - pdGainOverlap_t2);
664 for (k = 0; k < numXpdGain; k++)
665 gb[k] = (u16)min(gb_limit, gb[k]);
671 static void ath9k_adjust_pdadc_values(struct ath_hw *ah,
672 int8_t pwr_table_offset,
676 #define NUM_PDADC(diff) (AR5416_NUM_PDADC_VALUES - diff)
679 /* If this is a board that has a pwrTableOffset that differs from
680 * the default AR5416_PWR_TABLE_OFFSET_DB then the start of the
681 * pdadc vs pwr table needs to be adjusted prior to writing to the
684 if (AR_SREV_9280_20_OR_LATER(ah)) {
685 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
686 /* shift the table to start at the new offset */
687 for (k = 0; k < (u16)NUM_PDADC(diff); k++ ) {
688 pdadcValues[k] = pdadcValues[k + diff];
691 /* fill the back of the table */
692 for (k = (u16)NUM_PDADC(diff); k < NUM_PDADC(0); k++) {
693 pdadcValues[k] = pdadcValues[NUM_PDADC(diff)];
700 static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
701 struct ath9k_channel *chan,
702 int16_t *pTxPowerIndexOffset)
704 #define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
705 #define SM_PDGAIN_B(x, y) \
706 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
707 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
708 struct cal_data_per_freq *pRawDataset;
709 u8 *pCalBChans = NULL;
710 u16 pdGainOverlap_t2;
711 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
712 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
715 u16 numXpdGain, xpdMask;
716 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
717 u32 reg32, regOffset, regChainOffset;
719 int8_t pwr_table_offset;
721 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
722 xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
724 pwr_table_offset = ah->eep_ops->get_eeprom(ah, EEP_PWR_TABLE_OFFSET);
726 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
727 AR5416_EEP_MINOR_VER_2) {
729 pEepData->modalHeader[modalIdx].pdGainOverlap;
731 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
732 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
735 if (IS_CHAN_2GHZ(chan)) {
736 pCalBChans = pEepData->calFreqPier2G;
737 numPiers = AR5416_NUM_2G_CAL_PIERS;
739 pCalBChans = pEepData->calFreqPier5G;
740 numPiers = AR5416_NUM_5G_CAL_PIERS;
743 if (OLC_FOR_AR9280_20_LATER && IS_CHAN_2GHZ(chan)) {
744 pRawDataset = pEepData->calPierData2G[0];
745 ah->initPDADC = ((struct calDataPerFreqOpLoop *)
746 pRawDataset)->vpdPdg[0][0];
751 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
752 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
753 if (numXpdGain >= AR5416_NUM_PD_GAINS)
755 xpdGainValues[numXpdGain] =
756 (u16)(AR5416_PD_GAINS_IN_MASK - i);
761 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
762 (numXpdGain - 1) & 0x3);
763 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
765 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
767 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
770 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
771 if (AR_SREV_5416_20_OR_LATER(ah) &&
772 (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
774 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
776 regChainOffset = i * 0x1000;
778 if (pEepData->baseEepHeader.txMask & (1 << i)) {
779 if (IS_CHAN_2GHZ(chan))
780 pRawDataset = pEepData->calPierData2G[i];
782 pRawDataset = pEepData->calPierData5G[i];
785 if (OLC_FOR_AR9280_20_LATER) {
789 ath9k_get_txgain_index(ah, chan,
790 (struct calDataPerFreqOpLoop *)pRawDataset,
791 pCalBChans, numPiers, &txPower, &pcdacIdx);
792 ath9k_olc_get_pdadcs(ah, pcdacIdx,
793 txPower/2, pdadcValues);
795 ath9k_hw_get_gain_boundaries_pdadcs(ah,
797 pCalBChans, numPiers,
804 diff = ath9k_change_gain_boundary_setting(ah,
811 ENABLE_REGWRITE_BUFFER(ah);
813 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
814 if (OLC_FOR_AR9280_20_LATER) {
816 AR_PHY_TPCRG5 + regChainOffset,
818 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
819 SM_PD_GAIN(1) | SM_PD_GAIN(2) |
820 SM_PD_GAIN(3) | SM_PD_GAIN(4));
823 AR_PHY_TPCRG5 + regChainOffset,
825 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)|
834 ath9k_adjust_pdadc_values(ah, pwr_table_offset,
837 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
838 for (j = 0; j < 32; j++) {
839 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
840 ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
841 ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
842 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
843 REG_WRITE(ah, regOffset, reg32);
846 "PDADC (%d,%4x): %4.4x %8.8x\n",
847 i, regChainOffset, regOffset,
850 "PDADC: Chain %d | PDADC %3d "
851 "Value %3d | PDADC %3d Value %3d | "
852 "PDADC %3d Value %3d | PDADC %3d "
854 i, 4 * j, pdadcValues[4 * j],
855 4 * j + 1, pdadcValues[4 * j + 1],
856 4 * j + 2, pdadcValues[4 * j + 2],
857 4 * j + 3, pdadcValues[4 * j + 3]);
861 REGWRITE_BUFFER_FLUSH(ah);
865 *pTxPowerIndexOffset = 0;
870 static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
871 struct ath9k_channel *chan,
874 u16 AntennaReduction,
875 u16 twiceMaxRegulatoryPower,
878 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
879 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 9 /* 10*log10(3)*2 */
881 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
882 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
883 u16 twiceMaxEdgePower = MAX_RATE_POWER;
884 static const u16 tpScaleReductionTable[5] =
885 { 0, 3, 6, 9, MAX_RATE_POWER };
888 int16_t twiceLargestAntenna;
889 struct cal_ctl_data *rep;
890 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
893 struct cal_target_power_leg targetPowerOfdmExt = {
894 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
897 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
900 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
901 static const u16 ctlModesFor11a[] = {
902 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
904 static const u16 ctlModesFor11g[] = {
905 CTL_11B, CTL_11G, CTL_2GHT20,
906 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
911 struct chan_centers centers;
913 u16 twiceMinEdgePower;
915 tx_chainmask = ah->txchainmask;
917 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
919 twiceLargestAntenna = max(
920 pEepData->modalHeader
921 [IS_CHAN_2GHZ(chan)].antennaGainCh[0],
922 pEepData->modalHeader
923 [IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
925 twiceLargestAntenna = max((u8)twiceLargestAntenna,
926 pEepData->modalHeader
927 [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
929 twiceLargestAntenna = (int16_t)min(AntennaReduction -
930 twiceLargestAntenna, 0);
932 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
934 if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
935 maxRegAllowedPower -=
936 (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
939 scaledPower = min(powerLimit, maxRegAllowedPower);
941 switch (ar5416_get_ntxchains(tx_chainmask)) {
945 if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN)
946 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
951 if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN)
952 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
958 if (IS_CHAN_2GHZ(chan)) {
959 numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
960 SUB_NUM_CTL_MODES_AT_2G_40;
961 pCtlMode = ctlModesFor11g;
963 ath9k_hw_get_legacy_target_powers(ah, chan,
964 pEepData->calTargetPowerCck,
965 AR5416_NUM_2G_CCK_TARGET_POWERS,
966 &targetPowerCck, 4, 0);
967 ath9k_hw_get_legacy_target_powers(ah, chan,
968 pEepData->calTargetPower2G,
969 AR5416_NUM_2G_20_TARGET_POWERS,
970 &targetPowerOfdm, 4, 0);
971 ath9k_hw_get_target_powers(ah, chan,
972 pEepData->calTargetPower2GHT20,
973 AR5416_NUM_2G_20_TARGET_POWERS,
974 &targetPowerHt20, 8, 0);
976 if (IS_CHAN_HT40(chan)) {
977 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
978 ath9k_hw_get_target_powers(ah, chan,
979 pEepData->calTargetPower2GHT40,
980 AR5416_NUM_2G_40_TARGET_POWERS,
981 &targetPowerHt40, 8, 1);
982 ath9k_hw_get_legacy_target_powers(ah, chan,
983 pEepData->calTargetPowerCck,
984 AR5416_NUM_2G_CCK_TARGET_POWERS,
985 &targetPowerCckExt, 4, 1);
986 ath9k_hw_get_legacy_target_powers(ah, chan,
987 pEepData->calTargetPower2G,
988 AR5416_NUM_2G_20_TARGET_POWERS,
989 &targetPowerOfdmExt, 4, 1);
992 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
993 SUB_NUM_CTL_MODES_AT_5G_40;
994 pCtlMode = ctlModesFor11a;
996 ath9k_hw_get_legacy_target_powers(ah, chan,
997 pEepData->calTargetPower5G,
998 AR5416_NUM_5G_20_TARGET_POWERS,
999 &targetPowerOfdm, 4, 0);
1000 ath9k_hw_get_target_powers(ah, chan,
1001 pEepData->calTargetPower5GHT20,
1002 AR5416_NUM_5G_20_TARGET_POWERS,
1003 &targetPowerHt20, 8, 0);
1005 if (IS_CHAN_HT40(chan)) {
1006 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
1007 ath9k_hw_get_target_powers(ah, chan,
1008 pEepData->calTargetPower5GHT40,
1009 AR5416_NUM_5G_40_TARGET_POWERS,
1010 &targetPowerHt40, 8, 1);
1011 ath9k_hw_get_legacy_target_powers(ah, chan,
1012 pEepData->calTargetPower5G,
1013 AR5416_NUM_5G_20_TARGET_POWERS,
1014 &targetPowerOfdmExt, 4, 1);
1018 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
1019 int isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
1020 (pCtlMode[ctlMode] == CTL_2GHT40);
1022 freq = centers.synth_center;
1023 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
1024 freq = centers.ext_center;
1026 freq = centers.ctl_center;
1028 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
1029 ah->eep_ops->get_eeprom_rev(ah) <= 2)
1030 twiceMaxEdgePower = MAX_RATE_POWER;
1032 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
1033 if ((((cfgCtl & ~CTL_MODE_M) |
1034 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1035 pEepData->ctlIndex[i]) ||
1036 (((cfgCtl & ~CTL_MODE_M) |
1037 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1038 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
1039 rep = &(pEepData->ctlData[i]);
1041 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
1042 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1],
1043 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
1045 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
1046 twiceMaxEdgePower = min(twiceMaxEdgePower,
1049 twiceMaxEdgePower = twiceMinEdgePower;
1055 minCtlPower = min(twiceMaxEdgePower, scaledPower);
1057 switch (pCtlMode[ctlMode]) {
1059 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
1060 targetPowerCck.tPow2x[i] =
1061 min((u16)targetPowerCck.tPow2x[i],
1067 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
1068 targetPowerOfdm.tPow2x[i] =
1069 min((u16)targetPowerOfdm.tPow2x[i],
1075 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
1076 targetPowerHt20.tPow2x[i] =
1077 min((u16)targetPowerHt20.tPow2x[i],
1082 targetPowerCckExt.tPow2x[0] = min((u16)
1083 targetPowerCckExt.tPow2x[0],
1088 targetPowerOfdmExt.tPow2x[0] = min((u16)
1089 targetPowerOfdmExt.tPow2x[0],
1094 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1095 targetPowerHt40.tPow2x[i] =
1096 min((u16)targetPowerHt40.tPow2x[i],
1105 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
1106 ratesArray[rate18mb] = ratesArray[rate24mb] =
1107 targetPowerOfdm.tPow2x[0];
1108 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
1109 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
1110 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
1111 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
1113 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
1114 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
1116 if (IS_CHAN_2GHZ(chan)) {
1117 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
1118 ratesArray[rate2s] = ratesArray[rate2l] =
1119 targetPowerCck.tPow2x[1];
1120 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
1121 targetPowerCck.tPow2x[2];
1122 ratesArray[rate11s] = ratesArray[rate11l] =
1123 targetPowerCck.tPow2x[3];
1125 if (IS_CHAN_HT40(chan)) {
1126 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1127 ratesArray[rateHt40_0 + i] =
1128 targetPowerHt40.tPow2x[i];
1130 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
1131 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
1132 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
1133 if (IS_CHAN_2GHZ(chan)) {
1134 ratesArray[rateExtCck] =
1135 targetPowerCckExt.tPow2x[0];
1140 static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1141 struct ath9k_channel *chan,
1143 u8 twiceAntennaReduction,
1144 u8 twiceMaxRegulatoryPower,
1145 u8 powerLimit, int test)
1147 #define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
1148 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1149 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
1150 struct modal_eep_header *pModal =
1151 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
1152 int16_t ratesArray[Ar5416RateSize];
1153 int16_t txPowerIndexOffset = 0;
1154 u8 ht40PowerIncForPdadc = 2;
1155 unsigned int i, cck_ofdm_delta = 0;
1157 memset(ratesArray, 0, sizeof(ratesArray));
1159 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1160 AR5416_EEP_MINOR_VER_2) {
1161 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
1164 ath9k_hw_set_def_power_per_rate_table(ah, chan,
1165 &ratesArray[0], cfgCtl,
1166 twiceAntennaReduction,
1167 twiceMaxRegulatoryPower,
1170 ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset);
1172 regulatory->max_power_level = 0;
1173 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
1174 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
1175 if (ratesArray[i] > MAX_RATE_POWER)
1176 ratesArray[i] = MAX_RATE_POWER;
1177 if (ratesArray[i] > regulatory->max_power_level)
1178 regulatory->max_power_level = ratesArray[i];
1184 if (IS_CHAN_HT40(chan))
1186 else if (IS_CHAN_HT20(chan))
1189 regulatory->max_power_level = ratesArray[i];
1192 switch(ar5416_get_ntxchains(ah->txchainmask)) {
1196 regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
1199 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
1203 "Invalid chainmask configuration\n");
1210 if (AR_SREV_9280_20_OR_LATER(ah)) {
1211 for (i = 0; i < Ar5416RateSize; i++) {
1212 int8_t pwr_table_offset;
1214 pwr_table_offset = ah->eep_ops->get_eeprom(ah,
1215 EEP_PWR_TABLE_OFFSET);
1216 ratesArray[i] -= pwr_table_offset * 2;
1220 ENABLE_REGWRITE_BUFFER(ah);
1222 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
1223 ATH9K_POW_SM(ratesArray[rate18mb], 24)
1224 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
1225 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
1226 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
1227 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
1228 ATH9K_POW_SM(ratesArray[rate54mb], 24)
1229 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
1230 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
1231 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
1233 if (IS_CHAN_2GHZ(chan)) {
1234 if (OLC_FOR_AR9280_20_LATER) {
1236 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1237 ATH9K_POW_SM(RT_AR_DELTA(rate2s), 24)
1238 | ATH9K_POW_SM(RT_AR_DELTA(rate2l), 16)
1239 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1240 | ATH9K_POW_SM(RT_AR_DELTA(rate1l), 0));
1241 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1242 ATH9K_POW_SM(RT_AR_DELTA(rate11s), 24)
1243 | ATH9K_POW_SM(RT_AR_DELTA(rate11l), 16)
1244 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5s), 8)
1245 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5l), 0));
1247 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1248 ATH9K_POW_SM(ratesArray[rate2s], 24)
1249 | ATH9K_POW_SM(ratesArray[rate2l], 16)
1250 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1251 | ATH9K_POW_SM(ratesArray[rate1l], 0));
1252 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1253 ATH9K_POW_SM(ratesArray[rate11s], 24)
1254 | ATH9K_POW_SM(ratesArray[rate11l], 16)
1255 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
1256 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
1260 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
1261 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
1262 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
1263 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
1264 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
1265 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
1266 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
1267 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
1268 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
1269 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
1271 if (IS_CHAN_HT40(chan)) {
1272 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
1273 ATH9K_POW_SM(ratesArray[rateHt40_3] +
1274 ht40PowerIncForPdadc, 24)
1275 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
1276 ht40PowerIncForPdadc, 16)
1277 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
1278 ht40PowerIncForPdadc, 8)
1279 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
1280 ht40PowerIncForPdadc, 0));
1281 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
1282 ATH9K_POW_SM(ratesArray[rateHt40_7] +
1283 ht40PowerIncForPdadc, 24)
1284 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
1285 ht40PowerIncForPdadc, 16)
1286 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
1287 ht40PowerIncForPdadc, 8)
1288 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
1289 ht40PowerIncForPdadc, 0));
1290 if (OLC_FOR_AR9280_20_LATER) {
1291 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1292 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1293 | ATH9K_POW_SM(RT_AR_DELTA(rateExtCck), 16)
1294 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1295 | ATH9K_POW_SM(RT_AR_DELTA(rateDupCck), 0));
1297 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1298 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1299 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
1300 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1301 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
1305 REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
1306 ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
1307 | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
1309 REGWRITE_BUFFER_FLUSH(ah);
1312 static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, int is2GHz)
1314 #define EEP_DEF_SPURCHAN \
1315 (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
1317 u16 spur_val = AR_NO_SPUR;
1320 "Getting spur idx:%d is2Ghz:%d val:%x\n",
1321 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1323 switch (ah->config.spurmode) {
1326 case SPUR_ENABLE_IOCTL:
1327 spur_val = ah->config.spurchans[i][is2GHz];
1329 "Getting spur val from new loc. %d\n", spur_val);
1331 case SPUR_ENABLE_EEPROM:
1332 spur_val = EEP_DEF_SPURCHAN;
1338 #undef EEP_DEF_SPURCHAN
1341 const struct eeprom_ops eep_def_ops = {
1342 .check_eeprom = ath9k_hw_def_check_eeprom,
1343 .get_eeprom = ath9k_hw_def_get_eeprom,
1344 .fill_eeprom = ath9k_hw_def_fill_eeprom,
1345 .get_eeprom_ver = ath9k_hw_def_get_eeprom_ver,
1346 .get_eeprom_rev = ath9k_hw_def_get_eeprom_rev,
1347 .set_board_values = ath9k_hw_def_set_board_values,
1348 .set_addac = ath9k_hw_def_set_addac,
1349 .set_txpower = ath9k_hw_def_set_txpower,
1350 .get_spur_channel = ath9k_hw_def_get_spur_channel