2 * Copyright (c) 2010-2011 Atheros Communications Inc.
4 * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
5 * Original from Linux kernel 3.0.1
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23 #include "ar9003_phy.h"
25 static const int firstep_table[] =
26 /* level: 0 1 2 3 4 5 6 7 8 */
27 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
29 static const int cycpwrThr1_table[] =
30 /* level: 0 1 2 3 4 5 6 7 8 */
31 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
34 * register values to turn OFDM weak signal detection OFF
36 static const int m1ThreshLow_off = 127;
37 static const int m2ThreshLow_off = 127;
38 static const int m1Thresh_off = 127;
39 static const int m2Thresh_off = 127;
40 static const int m2CountThr_off = 31;
41 static const int m2CountThrLow_off = 63;
42 static const int m1ThreshLowExt_off = 127;
43 static const int m2ThreshLowExt_off = 127;
44 static const int m1ThreshExt_off = 127;
45 static const int m2ThreshExt_off = 127;
48 * ar9003_hw_set_channel - set channel on single-chip device
49 * @ah: atheros hardware structure
52 * This is the function to change channel on single-chip devices, that is
53 * all devices after ar9280.
55 * This function takes the channel value in MHz and sets
56 * hardware channel value. Assumes writes have been enabled to analog bus.
61 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
65 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
66 * (freq_ref = 40MHz/(24>>amodeRefSel))
68 * For 5GHz channels which are 5MHz spaced,
69 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
72 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
74 u16 bMode, fracMode = 0, aModeRefSel = 0;
75 u32 freq, channelSel = 0, reg32 = 0;
76 struct chan_centers centers;
79 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
80 freq = centers.synth_center;
82 if (freq < 4800) { /* 2 GHz, fractional mode */
83 if (AR_SREV_9485(ah)) {
87 * freq_ref = 40 / (refdiva >> amoderefsel); where refdiva=1 and amoderefsel=0
88 * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
89 * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
91 channelSel = (freq * 4) / 120;
92 chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
93 channelSel = (channelSel << 17) | chan_frac;
94 } else if (AR_SREV_9340(ah)) {
95 if (ah->is_clk_25mhz) {
98 channelSel = (freq * 2) / 75;
99 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
100 channelSel = (channelSel << 17) | chan_frac;
102 channelSel = CHANSEL_2G(freq) >> 1;
104 channelSel = CHANSEL_2G(freq);
108 if (AR_SREV_9340(ah) && ah->is_clk_25mhz) {
111 channelSel = (freq * 2) / 75;
112 chan_frac = ((freq % 75) * 0x20000) / 75;
113 channelSel = (channelSel << 17) | chan_frac;
115 channelSel = CHANSEL_5G(freq);
116 /* Doubler is ON, so, divide channelSel by 2. */
123 /* Enable fractional mode for all channels */
126 loadSynthChannel = 0;
128 reg32 = (bMode << 29);
129 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
131 /* Enable Long shift Select for Synthesizer */
132 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
133 AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
135 /* Program Synth. setting */
136 reg32 = (channelSel << 2) | (fracMode << 30) |
137 (aModeRefSel << 28) | (loadSynthChannel << 31);
138 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
140 /* Toggle Load Synth channel bit */
141 loadSynthChannel = 1;
142 reg32 = (channelSel << 2) | (fracMode << 30) |
143 (aModeRefSel << 28) | (loadSynthChannel << 31);
144 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
147 ah->curchan_rad_index = -1;
153 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
154 * @ah: atheros hardware structure
157 * For single-chip solutions. Converts to baseband spur frequency given the
158 * input channel frequency and compute register settings below.
160 * Spur mitigation for MRC CCK
162 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
163 struct ath9k_channel *chan)
165 static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
166 int cur_bb_spur, negative = 0, cck_spur_freq;
168 int range, max_spur_cnts, synth_freq;
169 u8 *spur_fbin_ptr = NULL;
172 * Need to verify range +/- 10 MHz in control channel, otherwise spur
173 * is out-of-band and can be ignored.
176 if (AR_SREV_9485(ah) || AR_SREV_9340(ah)) {
177 spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah,
179 if (spur_fbin_ptr[0] == 0) /* No spur */
182 if (IS_CHAN_HT40(chan)) {
184 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
185 AR_PHY_GC_DYN2040_PRI_CH) == 0)
186 synth_freq = chan->channel + 10;
188 synth_freq = chan->channel - 10;
191 synth_freq = chan->channel;
196 synth_freq = chan->channel;
199 for (i = 0; i < max_spur_cnts; i++) {
201 if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
202 cur_bb_spur = FBIN2FREQ(spur_fbin_ptr[i],
203 IS_CHAN_2GHZ(chan)) - synth_freq;
205 cur_bb_spur = spur_freq[i] - synth_freq;
207 if (cur_bb_spur < 0) {
209 cur_bb_spur = -cur_bb_spur;
211 if (cur_bb_spur < range) {
212 cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
215 cck_spur_freq = -cck_spur_freq;
217 cck_spur_freq = cck_spur_freq & 0xfffff;
219 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
220 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
221 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
222 AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
223 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
224 AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
226 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
227 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
229 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
230 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
237 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
238 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
239 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
240 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
241 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
242 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
245 /* Clean all spur register fields */
246 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
248 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
249 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
250 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
251 AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
252 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
253 AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
254 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
255 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
256 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
257 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
258 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
259 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
260 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
261 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
262 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
263 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
264 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
265 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
267 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
268 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
269 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
270 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
271 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
272 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
273 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
274 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
275 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
276 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
277 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
278 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
279 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
280 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
281 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
282 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
283 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
284 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
285 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
286 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
289 static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
292 int spur_delta_phase,
293 int spur_subchannel_sd)
297 /* OFDM Spur mitigation */
298 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
299 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
300 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
301 AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
302 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
303 AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
304 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
305 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
306 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
307 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
308 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
309 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
310 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
311 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
312 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
313 AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
314 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
315 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
317 if (REG_READ_FIELD(ah, AR_PHY_MODE,
318 AR_PHY_MODE_DYNAMIC) == 0x1)
319 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
320 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
322 mask_index = (freq_offset << 4) / 5;
324 mask_index = mask_index - 1;
326 mask_index = mask_index & 0x7f;
328 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
329 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
330 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
331 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
332 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
333 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
334 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
335 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
336 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
337 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
338 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
339 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
340 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
341 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
342 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
343 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
344 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
345 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
346 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
347 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
350 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
351 struct ath9k_channel *chan,
354 int spur_freq_sd = 0;
355 int spur_subchannel_sd = 0;
356 int spur_delta_phase = 0;
358 if (IS_CHAN_HT40(chan)) {
359 if (freq_offset < 0) {
360 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
361 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
362 spur_subchannel_sd = 1;
364 spur_subchannel_sd = 0;
366 spur_freq_sd = ((freq_offset + 10) << 9) / 11;
369 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
370 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
371 spur_subchannel_sd = 0;
373 spur_subchannel_sd = 1;
375 spur_freq_sd = ((freq_offset - 10) << 9) / 11;
379 spur_delta_phase = (freq_offset << 17) / 5;
382 spur_subchannel_sd = 0;
383 spur_freq_sd = (freq_offset << 9) /11;
384 spur_delta_phase = (freq_offset << 18) / 5;
387 spur_freq_sd = spur_freq_sd & 0x3ff;
388 spur_delta_phase = spur_delta_phase & 0xfffff;
390 ar9003_hw_spur_ofdm(ah,
397 /* Spur mitigation for OFDM */
398 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
399 struct ath9k_channel *chan)
407 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
409 if (IS_CHAN_5GHZ(chan)) {
410 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
414 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
418 if (spurChansPtr[0] == 0)
419 return; /* No spur in the mode */
421 if (IS_CHAN_HT40(chan)) {
423 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
424 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
425 synth_freq = chan->channel - 10;
427 synth_freq = chan->channel + 10;
430 synth_freq = chan->channel;
433 ar9003_hw_spur_ofdm_clear(ah);
435 for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
436 freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq;
437 if (abs(freq_offset) < range) {
438 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset);
444 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
445 struct ath9k_channel *chan)
447 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
448 ar9003_hw_spur_mitigate_ofdm(ah, chan);
451 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah __unused,
452 struct ath9k_channel *chan)
456 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
458 if (chan && IS_CHAN_HALF_RATE(chan))
459 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
460 else if (chan && IS_CHAN_QUARTER_RATE(chan))
461 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
463 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
468 static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
469 struct ath9k_channel *chan)
472 u32 enableDacFifo = 0;
475 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
477 /* Enable 11n HT, 20 MHz */
478 phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_WALSH |
479 AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
481 /* Configure baseband for dynamic 20/40 operation */
482 if (IS_CHAN_HT40(chan)) {
483 phymode |= AR_PHY_GC_DYN2040_EN;
484 /* Configure control (primary) channel at +-10MHz */
485 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
486 (chan->chanmode == CHANNEL_G_HT40PLUS))
487 phymode |= AR_PHY_GC_DYN2040_PRI_CH;
491 /* make sure we preserve INI settings */
492 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
493 /* turn off Green Field detection for STA for now */
494 phymode &= ~AR_PHY_GC_GF_DETECT_EN;
496 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
498 /* Configure MAC for 20/40 operation */
499 ath9k_hw_set11nmac2040(ah);
501 /* global transmit timeout (25 TUs default)*/
502 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
503 /* carrier sense timeout */
504 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
507 static void ar9003_hw_init_bb(struct ath_hw *ah,
508 struct ath9k_channel *chan)
513 * Wait for the frequency synth to settle (synth goes on
514 * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
515 * Value is in 100ns increments.
517 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
519 synthDelay = (4 * synthDelay) / 22;
523 /* Activate the PHY (includes baseband activate + synthesizer on) */
524 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
527 * There is an issue if the AP starts the calibration before
528 * the base band timeout completes. This could result in the
529 * rx_clear false triggering. As a workaround we add delay an
530 * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
533 udelay(synthDelay + BASE_ACTIVATE_DELAY);
536 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
540 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
541 AR_PHY_SWAP_ALT_CHAIN);
546 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
547 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
553 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
554 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
556 REG_WRITE(ah, AR_SELFGEN_MASK, tx);
559 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
560 AR_PHY_SWAP_ALT_CHAIN);
565 * Override INI values with chip specific configuration.
567 static void ar9003_hw_override_ini(struct ath_hw *ah)
572 * Set the RX_ABORT and RX_DIS and clear it only after
573 * RXE is set for MAC. This prevents frames with
574 * corrupted descriptor status.
576 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
579 * For AR9280 and above, there is a new feature that allows
580 * Multicast search based on both MAC Address and Key ID. By default,
581 * this feature is enabled. But since the driver is not using this
582 * feature, we switch it off; otherwise multicast search based on
583 * MAC addr only will fail.
585 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
586 REG_WRITE(ah, AR_PCU_MISC_MODE2,
587 val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
590 static void ar9003_hw_prog_ini(struct ath_hw *ah,
591 struct ar5416IniArray *iniArr,
594 unsigned int i, regWrites = 0;
596 /* New INI format: Array may be undefined (pre, core, post arrays) */
597 if (!iniArr->ia_array)
601 * New INI format: Pre, core, and post arrays for a given subsystem
602 * may be modal (> 2 columns) or non-modal (2 columns). Determine if
603 * the array is non-modal and force the column to 1.
605 if ((unsigned int)column >= iniArr->ia_columns)
608 for (i = 0; i < iniArr->ia_rows; i++) {
609 u32 reg = INI_RA(iniArr, i, 0);
610 u32 val = INI_RA(iniArr, i, column);
612 REG_WRITE(ah, reg, val);
618 static int ar9003_hw_process_ini(struct ath_hw *ah,
619 struct ath9k_channel *chan)
621 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
622 unsigned int regWrites = 0, i;
623 struct net80211_channel *channel = chan->chan;
626 switch (chan->chanmode) {
631 case CHANNEL_A_HT40PLUS:
632 case CHANNEL_A_HT40MINUS:
640 case CHANNEL_G_HT40PLUS:
641 case CHANNEL_G_HT40MINUS:
649 for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
650 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
651 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
652 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
653 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
656 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
657 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
660 * For 5GHz channels requiring Fast Clock, apply
661 * different modal values.
663 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
664 REG_WRITE_ARRAY(&ah->iniModesAdditional,
665 modesIndex, regWrites);
667 if (AR_SREV_9340(ah) && !ah->is_clk_25mhz)
668 REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites);
670 ar9003_hw_override_ini(ah);
671 ar9003_hw_set_channel_regs(ah, chan);
672 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
675 ah->eep_ops->set_txpower(ah, chan,
676 ath9k_regd_get_ctl(regulatory, chan),
678 channel->maxpower * 2,
679 min((u32) MAX_RATE_POWER,
680 (u32) regulatory->power_limit), 0);
685 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
686 struct ath9k_channel *chan)
693 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
694 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
696 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
697 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
699 REG_WRITE(ah, AR_PHY_MODE, rfMode);
702 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
704 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
707 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
708 struct ath9k_channel *chan)
710 u32 coef_scaled, ds_coef_exp, ds_coef_man;
711 u32 clockMhzScaled = 0x64000000;
712 struct chan_centers centers;
715 * half and quarter rate can divide the scaled clock by 2 or 4
716 * scale for selected channel bandwidth
718 if (IS_CHAN_HALF_RATE(chan))
719 clockMhzScaled = clockMhzScaled >> 1;
720 else if (IS_CHAN_QUARTER_RATE(chan))
721 clockMhzScaled = clockMhzScaled >> 2;
724 * ALGO -> coef = 1e8/fcarrier*fclock/40;
725 * scaled coef to provide precision for this floating calculation
727 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
728 coef_scaled = clockMhzScaled / centers.synth_center;
730 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
733 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
734 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
735 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
736 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
740 * scaled coeff is 9/10 that of normal coeff
742 coef_scaled = (9 * coef_scaled) / 10;
744 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
748 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
749 AR_PHY_SGI_DSC_MAN, ds_coef_man);
750 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
751 AR_PHY_SGI_DSC_EXP, ds_coef_exp);
754 static int ar9003_hw_rfbus_req(struct ath_hw *ah)
756 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
757 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
758 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
762 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
763 * Read the phy active delay register. Value is in 100ns increments.
765 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
767 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
768 if (IS_CHAN_B(ah->curchan))
769 synthDelay = (4 * synthDelay) / 22;
773 udelay(synthDelay + BASE_ACTIVATE_DELAY);
775 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
778 static void ar9003_hw_set_diversity(struct ath_hw *ah, int value)
780 u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
782 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
784 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
785 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
788 static int ar9003_hw_ani_control(struct ath_hw *ah,
789 enum ath9k_ani_cmd cmd, int param)
791 struct ath9k_channel *chan = ah->curchan;
792 struct ar5416AniState *aniState = &chan->ani;
795 switch (cmd & ah->ani_function) {
796 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
798 * on == 1 means ofdm weak signal detection is ON
799 * on == 1 is the default, for less noise immunity
801 * on == 0 means ofdm weak signal detection is OFF
802 * on == 0 means more noise imm
804 u32 on = param ? 1 : 0;
806 * make register setting for default
807 * (weak sig detect ON) come from INI file
809 int m1ThreshLow = on ?
810 aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
811 int m2ThreshLow = on ?
812 aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
814 aniState->iniDef.m1Thresh : m1Thresh_off;
816 aniState->iniDef.m2Thresh : m2Thresh_off;
817 int m2CountThr = on ?
818 aniState->iniDef.m2CountThr : m2CountThr_off;
819 int m2CountThrLow = on ?
820 aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
821 int m1ThreshLowExt = on ?
822 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
823 int m2ThreshLowExt = on ?
824 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
825 int m1ThreshExt = on ?
826 aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
827 int m2ThreshExt = on ?
828 aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
830 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
831 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
833 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
834 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
836 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
837 AR_PHY_SFCORR_M1_THRESH, m1Thresh);
838 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
839 AR_PHY_SFCORR_M2_THRESH, m2Thresh);
840 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
841 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
842 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
843 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
846 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
847 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
848 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
849 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
850 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
851 AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
852 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
853 AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
856 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
857 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
859 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
860 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
862 if (on != aniState->ofdmWeakSigDetect) {
864 "** ch %d: ofdm weak signal: %s=>%s\n",
866 aniState->ofdmWeakSigDetect ?
870 ah->stats.ast_ani_ofdmon++;
872 ah->stats.ast_ani_ofdmoff++;
873 aniState->ofdmWeakSigDetect = on;
877 case ATH9K_ANI_FIRSTEP_LEVEL:{
880 if (level >= ARRAY_SIZE(firstep_table)) {
882 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%d > %zd)\n",
883 level, ARRAY_SIZE(firstep_table));
888 * make register setting relative to default
889 * from INI file & cap value
891 value = firstep_table[level] -
892 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
893 aniState->iniDef.firstep;
894 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
895 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
896 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
897 value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
898 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
899 AR_PHY_FIND_SIG_FIRSTEP,
902 * we need to set first step low register too
903 * make register setting relative to default
904 * from INI file & cap value
906 value2 = firstep_table[level] -
907 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
908 aniState->iniDef.firstepLow;
909 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
910 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
911 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
912 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
914 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
915 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
917 if (level != aniState->firstepLevel) {
919 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
921 aniState->firstepLevel,
923 ATH9K_ANI_FIRSTEP_LVL_NEW,
925 aniState->iniDef.firstep);
927 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
929 aniState->firstepLevel,
931 ATH9K_ANI_FIRSTEP_LVL_NEW,
933 aniState->iniDef.firstepLow);
934 if (level > aniState->firstepLevel)
935 ah->stats.ast_ani_stepup++;
936 else if (level < aniState->firstepLevel)
937 ah->stats.ast_ani_stepdown++;
938 aniState->firstepLevel = level;
942 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
945 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
947 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%d > %zd)\n",
948 level, ARRAY_SIZE(cycpwrThr1_table));
952 * make register setting relative to default
953 * from INI file & cap value
955 value = cycpwrThr1_table[level] -
956 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
957 aniState->iniDef.cycpwrThr1;
958 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
959 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
960 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
961 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
962 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
963 AR_PHY_TIMING5_CYCPWR_THR1,
967 * set AR_PHY_EXT_CCA for extension channel
968 * make register setting relative to default
969 * from INI file & cap value
971 value2 = cycpwrThr1_table[level] -
972 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
973 aniState->iniDef.cycpwrThr1Ext;
974 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
975 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
976 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
977 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
978 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
979 AR_PHY_EXT_CYCPWR_THR1, value2);
981 if (level != aniState->spurImmunityLevel) {
983 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
985 aniState->spurImmunityLevel,
987 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
989 aniState->iniDef.cycpwrThr1);
991 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
993 aniState->spurImmunityLevel,
995 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
997 aniState->iniDef.cycpwrThr1Ext);
998 if (level > aniState->spurImmunityLevel)
999 ah->stats.ast_ani_spurup++;
1000 else if (level < aniState->spurImmunityLevel)
1001 ah->stats.ast_ani_spurdown++;
1002 aniState->spurImmunityLevel = level;
1006 case ATH9K_ANI_MRC_CCK:{
1008 * is_on == 1 means MRC CCK ON (default, less noise imm)
1009 * is_on == 0 means MRC CCK is OFF (more noise imm)
1011 int is_on = param ? 1 : 0;
1012 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1013 AR_PHY_MRC_CCK_ENABLE, is_on);
1014 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1015 AR_PHY_MRC_CCK_MUX_REG, is_on);
1016 if (!(is_on != aniState->mrcCCKOff)) {
1018 "** ch %d: MRC CCK: %s=>%s\n",
1020 !aniState->mrcCCKOff ? "on" : "off",
1021 is_on ? "on" : "off");
1023 ah->stats.ast_ani_ccklow++;
1025 ah->stats.ast_ani_cckhigh++;
1026 aniState->mrcCCKOff = !is_on;
1030 case ATH9K_ANI_PRESENT:
1033 DBG2("ath9k: invalid cmd %d\n", cmd);
1038 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1039 aniState->spurImmunityLevel,
1040 aniState->ofdmWeakSigDetect ? "on" : "off",
1041 aniState->firstepLevel,
1042 !aniState->mrcCCKOff ? "on" : "off",
1043 aniState->listenTime,
1044 aniState->ofdmPhyErrCount,
1045 aniState->cckPhyErrCount);
1049 static void ar9003_hw_do_getnf(struct ath_hw *ah,
1050 int16_t nfarray[NUM_NF_READINGS])
1052 #define AR_PHY_CH_MINCCA_PWR 0x1FF00000
1053 #define AR_PHY_CH_MINCCA_PWR_S 20
1054 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1055 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16
1060 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1061 if (ah->rxchainmask & BIT(i)) {
1062 nf = MS(REG_READ(ah, ah->nf_regs[i]),
1063 AR_PHY_CH_MINCCA_PWR);
1064 nfarray[i] = sign_extend32(nf, 8);
1066 if (IS_CHAN_HT40(ah->curchan)) {
1067 u8 ext_idx = AR9300_MAX_CHAINS + i;
1069 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1070 AR_PHY_CH_EXT_MINCCA_PWR);
1071 nfarray[ext_idx] = sign_extend32(nf, 8);
1077 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1079 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1080 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1081 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1082 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1083 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1084 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
1088 * Initialize the ANI register values with default (ini) values.
1089 * This routine is called during a (full) hardware reset after
1090 * all the registers are initialised from the INI.
1092 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1094 struct ar5416AniState *aniState;
1095 struct ath9k_channel *chan = ah->curchan;
1096 struct ath9k_ani_default *iniDef;
1099 aniState = &ah->curchan->ani;
1100 iniDef = &aniState->iniDef;
1103 "ver %d.%d chan %d Mhz/0x%x\n",
1104 ah->hw_version.macVersion,
1105 ah->hw_version.macRev,
1107 chan->channelFlags);
1109 val = REG_READ(ah, AR_PHY_SFCORR);
1110 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1111 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1112 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1114 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1115 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1116 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1117 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1119 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1120 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1121 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1122 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1123 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1124 iniDef->firstep = REG_READ_FIELD(ah,
1126 AR_PHY_FIND_SIG_FIRSTEP);
1127 iniDef->firstepLow = REG_READ_FIELD(ah,
1128 AR_PHY_FIND_SIG_LOW,
1129 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1130 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1132 AR_PHY_TIMING5_CYCPWR_THR1);
1133 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1135 AR_PHY_EXT_CYCPWR_THR1);
1137 /* these levels just got reset to defaults by the INI */
1138 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
1139 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
1140 aniState->ofdmWeakSigDetect = ATH9K_ANI_USE_OFDM_WEAK_SIG;
1141 aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK;
1144 static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1145 struct ath_hw_radar_conf *conf)
1147 u32 radar_0 = 0, radar_1 = 0;
1150 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1154 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1155 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1156 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1157 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1158 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1159 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1161 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1162 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1163 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1164 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1165 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1167 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1168 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1169 if (conf->ext_channel)
1170 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1172 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1175 static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1177 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1179 conf->fir_power = -28;
1180 conf->radar_rssi = 0;
1181 conf->pulse_height = 10;
1182 conf->pulse_rssi = 24;
1183 conf->pulse_inband = 8;
1184 conf->pulse_maxlen = 255;
1185 conf->pulse_inband_step = 12;
1186 conf->radar_inband = 8;
1189 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1190 struct ath_hw_antcomb_conf *antconf)
1194 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1195 antconf->main_lna_conf = (regval & AR_PHY_9485_ANT_DIV_MAIN_LNACONF) >>
1196 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S;
1197 antconf->alt_lna_conf = (regval & AR_PHY_9485_ANT_DIV_ALT_LNACONF) >>
1198 AR_PHY_9485_ANT_DIV_ALT_LNACONF_S;
1199 antconf->fast_div_bias = (regval & AR_PHY_9485_ANT_FAST_DIV_BIAS) >>
1200 AR_PHY_9485_ANT_FAST_DIV_BIAS_S;
1201 antconf->lna1_lna2_delta = -9;
1202 antconf->div_group = 2;
1205 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1206 struct ath_hw_antcomb_conf *antconf)
1210 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1211 regval &= ~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
1212 AR_PHY_9485_ANT_DIV_ALT_LNACONF |
1213 AR_PHY_9485_ANT_FAST_DIV_BIAS |
1214 AR_PHY_9485_ANT_DIV_MAIN_GAINTB |
1215 AR_PHY_9485_ANT_DIV_ALT_GAINTB);
1216 regval |= ((antconf->main_lna_conf <<
1217 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S)
1218 & AR_PHY_9485_ANT_DIV_MAIN_LNACONF);
1219 regval |= ((antconf->alt_lna_conf << AR_PHY_9485_ANT_DIV_ALT_LNACONF_S)
1220 & AR_PHY_9485_ANT_DIV_ALT_LNACONF);
1221 regval |= ((antconf->fast_div_bias << AR_PHY_9485_ANT_FAST_DIV_BIAS_S)
1222 & AR_PHY_9485_ANT_FAST_DIV_BIAS);
1223 regval |= ((antconf->main_gaintb << AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S)
1224 & AR_PHY_9485_ANT_DIV_MAIN_GAINTB);
1225 regval |= ((antconf->alt_gaintb << AR_PHY_9485_ANT_DIV_ALT_GAINTB_S)
1226 & AR_PHY_9485_ANT_DIV_ALT_GAINTB);
1228 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1231 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1233 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1234 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1235 static const u32 ar9300_cca_regs[6] = {
1244 priv_ops->rf_set_freq = ar9003_hw_set_channel;
1245 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1246 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1247 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1248 priv_ops->init_bb = ar9003_hw_init_bb;
1249 priv_ops->process_ini = ar9003_hw_process_ini;
1250 priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1251 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1252 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1253 priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1254 priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1255 priv_ops->set_diversity = ar9003_hw_set_diversity;
1256 priv_ops->ani_control = ar9003_hw_ani_control;
1257 priv_ops->do_getnf = ar9003_hw_do_getnf;
1258 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
1259 priv_ops->set_radar_params = ar9003_hw_set_radar_params;
1261 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
1262 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
1264 ar9003_hw_set_nf_limits(ah);
1265 ar9003_hw_set_radar_conf(ah);
1266 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
1269 void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
1273 val = REG_READ(ah, AR_PHY_RESTART);
1274 val &= ~AR_PHY_RESTART_ENA;
1276 REG_WRITE(ah, AR_PHY_RESTART, val);