2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
5 * Original from Linux kernel 3.0.1
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
24 #define AR_BufLen 0x00000fff
26 static void ar9002_hw_rx_enable(struct ath_hw *ah)
28 REG_WRITE(ah, AR_CR, AR_CR_RXE);
31 static void ar9002_hw_set_desc_link(void *ds, u32 ds_link)
33 ((struct ath_desc*) ds)->ds_link = ds_link;
36 static void ar9002_hw_get_desc_link(void *ds, u32 **ds_link)
38 *ds_link = &((struct ath_desc *)ds)->ds_link;
41 static int ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
45 struct ath9k_hw_capabilities *pCap = &ah->caps;
49 if (!AR_SREV_9100(ah) && (ah->ah_ier & AR_IER_ENABLE)) {
50 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
51 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
52 == AR_RTC_STATUS_ON) {
53 isr = REG_READ(ah, AR_ISR);
57 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
62 if (!isr && !sync_cause)
66 isr = REG_READ(ah, AR_ISR);
70 if (isr & AR_ISR_BCNMISC) {
72 isr2 = REG_READ(ah, AR_ISR_S2);
73 if (isr2 & AR_ISR_S2_TIM)
74 mask2 |= ATH9K_INT_TIM;
75 if (isr2 & AR_ISR_S2_DTIM)
76 mask2 |= ATH9K_INT_DTIM;
77 if (isr2 & AR_ISR_S2_DTIMSYNC)
78 mask2 |= ATH9K_INT_DTIMSYNC;
79 if (isr2 & (AR_ISR_S2_CABEND))
80 mask2 |= ATH9K_INT_CABEND;
81 if (isr2 & AR_ISR_S2_GTT)
82 mask2 |= ATH9K_INT_GTT;
83 if (isr2 & AR_ISR_S2_CST)
84 mask2 |= ATH9K_INT_CST;
85 if (isr2 & AR_ISR_S2_TSFOOR)
86 mask2 |= ATH9K_INT_TSFOOR;
89 isr = REG_READ(ah, AR_ISR_RAC);
90 if (isr == 0xffffffff) {
95 *masked = isr & ATH9K_INT_COMMON;
97 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM |
98 AR_ISR_RXOK | AR_ISR_RXERR))
99 *masked |= ATH9K_INT_RX;
102 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
106 *masked |= ATH9K_INT_TX;
108 s0_s = REG_READ(ah, AR_ISR_S0_S);
109 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
110 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
112 s1_s = REG_READ(ah, AR_ISR_S1_S);
113 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
114 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
117 if (isr & AR_ISR_RXORN) {
119 "receive FIFO overrun interrupt\n");
125 if (AR_SREV_9100(ah))
128 if (isr & AR_ISR_GENTMR) {
131 s5_s = REG_READ(ah, AR_ISR_S5_S);
132 ah->intr_gen_timer_trigger =
133 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
135 ah->intr_gen_timer_thresh =
136 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
138 if (ah->intr_gen_timer_trigger)
139 *masked |= ATH9K_INT_GENTIMER;
141 if ((s5_s & AR_ISR_S5_TIM_TIMER) &&
142 !(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
143 *masked |= ATH9K_INT_TIM_TIMER;
149 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
153 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
155 "received PCI FATAL interrupt\n");
157 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
159 "received PCI PERR interrupt\n");
161 *masked |= ATH9K_INT_FATAL;
163 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
165 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
166 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
167 REG_WRITE(ah, AR_RC, 0);
168 *masked |= ATH9K_INT_FATAL;
170 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
172 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
175 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
176 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
182 static void ar9002_hw_fill_txdesc(struct ath_hw *ah __unused, void *ds, u32 seglen,
183 int is_firstseg, int is_lastseg,
184 const void *ds0, u32 buf_addr,
185 unsigned int qcu __unused)
187 struct ar5416_desc *ads = AR5416DESC(ds);
189 ads->ds_data = buf_addr;
192 ads->ds_ctl1 |= seglen | (is_lastseg ? 0 : AR_TxMore);
193 } else if (is_lastseg) {
195 ads->ds_ctl1 = seglen;
196 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
197 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
200 ads->ds_ctl1 = seglen | AR_TxMore;
204 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
205 ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
206 ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
207 ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
208 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
211 static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds,
212 struct ath_tx_status *ts)
214 struct ar5416_desc *ads = AR5416DESC(ds);
217 status = *(volatile typeof(ads->ds_txstatus9) *)&(ads->ds_txstatus9);
218 if ((status & AR_TxDone) == 0)
221 ts->ts_tstamp = ads->AR_SendTimestamp;
225 if (status & AR_TxOpExceeded)
226 ts->ts_status |= ATH9K_TXERR_XTXOP;
227 ts->tid = MS(status, AR_TxTid);
228 ts->ts_rateindex = MS(status, AR_FinalTxIdx);
229 ts->ts_seqnum = MS(status, AR_SeqNum);
231 status = *(volatile typeof(ads->ds_txstatus0) *)&(ads->ds_txstatus0);
232 ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00);
233 ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01);
234 ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02);
235 if (status & AR_TxBaStatus) {
236 ts->ts_flags |= ATH9K_TX_BA;
237 ts->ba_low = ads->AR_BaBitmapLow;
238 ts->ba_high = ads->AR_BaBitmapHigh;
241 status = *(volatile typeof(ads->ds_txstatus1) *)&(ads->ds_txstatus1);
242 if (status & AR_FrmXmitOK)
243 ts->ts_status |= ATH9K_TX_ACKED;
245 if (status & AR_ExcessiveRetries)
246 ts->ts_status |= ATH9K_TXERR_XRETRY;
247 if (status & AR_Filtered)
248 ts->ts_status |= ATH9K_TXERR_FILT;
249 if (status & AR_FIFOUnderrun) {
250 ts->ts_status |= ATH9K_TXERR_FIFO;
251 ath9k_hw_updatetxtriglevel(ah, 1);
254 if (status & AR_TxTimerExpired)
255 ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
256 if (status & AR_DescCfgErr)
257 ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
258 if (status & AR_TxDataUnderrun) {
259 ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
260 ath9k_hw_updatetxtriglevel(ah, 1);
262 if (status & AR_TxDelimUnderrun) {
263 ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
264 ath9k_hw_updatetxtriglevel(ah, 1);
266 ts->ts_shortretry = MS(status, AR_RTSFailCnt);
267 ts->ts_longretry = MS(status, AR_DataFailCnt);
268 ts->ts_virtcol = MS(status, AR_VirtRetryCnt);
270 status = *(volatile typeof(ads->ds_txstatus5) *)&(ads->ds_txstatus5);
271 ts->ts_rssi = MS(status, AR_TxRSSICombined);
272 ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10);
273 ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11);
274 ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12);
276 ts->evm0 = ads->AR_TxEVM0;
277 ts->evm1 = ads->AR_TxEVM1;
278 ts->evm2 = ads->AR_TxEVM2;
283 static void ar9002_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
284 u32 pktLen, enum ath9k_pkt_type type,
285 u32 txPower, u32 keyIx,
286 enum ath9k_key_type keyType, u32 flags)
288 struct ar5416_desc *ads = AR5416DESC(ds);
293 ads->ds_ctl0 = (pktLen & AR_FrameLen)
294 | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
295 | SM(txPower, AR_XmitPower)
296 | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
297 | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
298 | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
301 (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
302 | SM(type, AR_FrameType)
303 | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
304 | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
305 | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
307 ads->ds_ctl6 = SM(keyType, AR_EncrType);
309 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
317 static void ar9002_hw_set_clrdmask(struct ath_hw *ah __unused, void *ds, int val)
319 struct ar5416_desc *ads = AR5416DESC(ds);
322 ads->ds_ctl0 |= AR_ClrDestMask;
324 ads->ds_ctl0 &= ~AR_ClrDestMask;
327 static void ar9002_hw_set11n_ratescenario(struct ath_hw *ah __unused, void *ds,
329 u32 durUpdateEn, u32 rtsctsRate,
330 u32 rtsctsDuration __unused,
331 struct ath9k_11n_rate_series series[],
332 u32 nseries __unused, u32 flags)
334 struct ar5416_desc *ads = AR5416DESC(ds);
335 struct ar5416_desc *last_ads = AR5416DESC(lastds);
338 if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
339 ds_ctl0 = ads->ds_ctl0;
341 if (flags & ATH9K_TXDESC_RTSENA) {
342 ds_ctl0 &= ~AR_CTSEnable;
343 ds_ctl0 |= AR_RTSEnable;
345 ds_ctl0 &= ~AR_RTSEnable;
346 ds_ctl0 |= AR_CTSEnable;
349 ads->ds_ctl0 = ds_ctl0;
352 (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
355 ads->ds_ctl2 = set11nTries(series, 0)
356 | set11nTries(series, 1)
357 | set11nTries(series, 2)
358 | set11nTries(series, 3)
359 | (durUpdateEn ? AR_DurUpdateEna : 0)
360 | SM(0, AR_BurstDur);
362 ads->ds_ctl3 = set11nRate(series, 0)
363 | set11nRate(series, 1)
364 | set11nRate(series, 2)
365 | set11nRate(series, 3);
367 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
368 | set11nPktDurRTSCTS(series, 1);
370 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
371 | set11nPktDurRTSCTS(series, 3);
373 ads->ds_ctl7 = set11nRateFlags(series, 0)
374 | set11nRateFlags(series, 1)
375 | set11nRateFlags(series, 2)
376 | set11nRateFlags(series, 3)
377 | SM(rtsctsRate, AR_RTSCTSRate);
378 last_ads->ds_ctl2 = ads->ds_ctl2;
379 last_ads->ds_ctl3 = ads->ds_ctl3;
382 static void ar9002_hw_set11n_aggr_first(struct ath_hw *ah __unused, void *ds,
385 struct ar5416_desc *ads = AR5416DESC(ds);
387 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
388 ads->ds_ctl6 &= ~AR_AggrLen;
389 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
392 static void ar9002_hw_set11n_aggr_middle(struct ath_hw *ah __unused, void *ds,
395 struct ar5416_desc *ads = AR5416DESC(ds);
398 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
401 ctl6 &= ~AR_PadDelim;
402 ctl6 |= SM(numDelims, AR_PadDelim);
406 static void ar9002_hw_set11n_aggr_last(struct ath_hw *ah __unused, void *ds)
408 struct ar5416_desc *ads = AR5416DESC(ds);
410 ads->ds_ctl1 |= AR_IsAggr;
411 ads->ds_ctl1 &= ~AR_MoreAggr;
412 ads->ds_ctl6 &= ~AR_PadDelim;
415 static void ar9002_hw_clr11n_aggr(struct ath_hw *ah __unused, void *ds)
417 struct ar5416_desc *ads = AR5416DESC(ds);
419 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
422 void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
425 struct ar5416_desc *ads = AR5416DESC(ds);
426 struct ath9k_hw_capabilities *pCap = &ah->caps;
428 ads->ds_ctl1 = size & AR_BufLen;
429 if (flags & ATH9K_RXDESC_INTREQ)
430 ads->ds_ctl1 |= AR_RxIntrReq;
432 ads->ds_rxstatus8 &= ~AR_RxDone;
433 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
434 memset(&(ads->u), 0, sizeof(ads->u));
437 void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
439 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
441 ops->rx_enable = ar9002_hw_rx_enable;
442 ops->set_desc_link = ar9002_hw_set_desc_link;
443 ops->get_desc_link = ar9002_hw_get_desc_link;
444 ops->get_isr = ar9002_hw_get_isr;
445 ops->fill_txdesc = ar9002_hw_fill_txdesc;
446 ops->proc_txdesc = ar9002_hw_proc_txdesc;
447 ops->set11n_txdesc = ar9002_hw_set11n_txdesc;
448 ops->set11n_ratescenario = ar9002_hw_set11n_ratescenario;
449 ops->set11n_aggr_first = ar9002_hw_set11n_aggr_first;
450 ops->set11n_aggr_middle = ar9002_hw_set11n_aggr_middle;
451 ops->set11n_aggr_last = ar9002_hw_set11n_aggr_last;
452 ops->clr11n_aggr = ar9002_hw_clr11n_aggr;
453 ops->set_clrdmask = ar9002_hw_set_clrdmask;