5 * Following are the generic definitions for the ADDI-DATA timer/counter/
6 * watchdog (TCW) registers and bits. Some of the registers are not used
7 * depending on the use of the TCW.
10 #define ADDI_TCW_VAL_REG 0x00
12 #define ADDI_TCW_SYNC_REG 0x00
13 #define ADDI_TCW_SYNC_CTR_TRIG (1 << 8)
14 #define ADDI_TCW_SYNC_CTR_DIS (1 << 7)
15 #define ADDI_TCW_SYNC_CTR_ENA (1 << 6)
16 #define ADDI_TCW_SYNC_TIMER_TRIG (1 << 5)
17 #define ADDI_TCW_SYNC_TIMER_DIS (1 << 4)
18 #define ADDI_TCW_SYNC_TIMER_ENA (1 << 3)
19 #define ADDI_TCW_SYNC_WDOG_TRIG (1 << 2)
20 #define ADDI_TCW_SYNC_WDOG_DIS (1 << 1)
21 #define ADDI_TCW_SYNC_WDOG_ENA (1 << 0)
23 #define ADDI_TCW_RELOAD_REG 0x04
25 #define ADDI_TCW_TIMEBASE_REG 0x08
27 #define ADDI_TCW_CTRL_REG 0x0c
28 #define ADDI_TCW_CTRL_EXT_CLK_STATUS (1 << 21)
29 #define ADDI_TCW_CTRL_CASCADE (1 << 20)
30 #define ADDI_TCW_CTRL_CNTR_ENA (1 << 19)
31 #define ADDI_TCW_CTRL_CNT_UP (1 << 18)
32 #define ADDI_TCW_CTRL_EXT_CLK(x) ((x) << 16)
33 #define ADDI_TCW_CTRL_OUT(x) ((x) << 11)
34 #define ADDI_TCW_CTRL_GATE (1 << 10)
35 #define ADDI_TCW_CTRL_TRIG (1 << 9)
36 #define ADDI_TCW_CTRL_EXT_GATE(x) ((x) << 7)
37 #define ADDI_TCW_CTRL_EXT_TRIG(x) ((x) << 5)
38 #define ADDI_TCW_CTRL_TIMER_ENA (1 << 4)
39 #define ADDI_TCW_CTRL_RESET_ENA (1 << 3)
40 #define ADDI_TCW_CTRL_WARN_ENA (1 << 2)
41 #define ADDI_TCW_CTRL_IRQ_ENA (1 << 1)
42 #define ADDI_TCW_CTRL_ENA (1 << 0)
44 #define ADDI_TCW_STATUS_REG 0x10
45 #define ADDI_TCW_STATUS_SOFT_CLR (1 << 3)
46 #define ADDI_TCW_STATUS_SOFT_TRIG (1 << 1)
47 #define ADDI_TCW_STATUS_OVERFLOW (1 << 0)
49 #define ADDI_TCW_IRQ_REG 0x14
50 #define ADDI_TCW_IRQ (1 << 0)
52 #define ADDI_TCW_WARN_TIMEVAL_REG 0x18
54 #define ADDI_TCW_WARN_TIMEBASE_REG 0x1c