1 /* Digital Input IRQ Function Selection */
2 #define APCI1564_DI_INT_OR (0 << 1)
3 #define APCI1564_DI_INT_AND (1 << 1)
5 /* Digital Input Interrupt Enable Disable. */
6 #define APCI1564_DI_INT_ENABLE 0x4
7 #define APCI1564_DI_INT_DISABLE 0xfffffffb
9 /* Digital Output Interrupt Enable Disable. */
10 #define APCI1564_DO_VCC_INT_ENABLE 0x1
11 #define APCI1564_DO_VCC_INT_DISABLE 0xfffffffe
12 #define APCI1564_DO_CC_INT_ENABLE 0x2
13 #define APCI1564_DO_CC_INT_DISABLE 0xfffffffd
15 /* TIMER COUNTER WATCHDOG DEFINES */
16 #define ADDIDATA_TIMER 0
17 #define ADDIDATA_COUNTER 1
18 #define ADDIDATA_WATCHDOG 2
20 static int apci1564_timer_insn_config(struct comedi_device *dev,
21 struct comedi_subdevice *s,
22 struct comedi_insn *insn,
25 struct apci1564_private *devpriv = dev->private;
28 devpriv->tsk_current = current;
30 /* First Stop The Timer */
31 ctrl = inl(devpriv->timer + ADDI_TCW_CTRL_REG);
34 outl(ctrl, devpriv->timer + ADDI_TCW_CTRL_REG);
37 /* Enable timer int & disable all the other int sources */
38 outl(0x02, devpriv->timer + ADDI_TCW_CTRL_REG);
39 outl(0x0, dev->iobase + APCI1564_DI_IRQ_REG);
40 outl(0x0, dev->iobase + APCI1564_DO_IRQ_REG);
41 outl(0x0, dev->iobase + APCI1564_WDOG_IRQ_REG);
42 if (devpriv->counters) {
45 iobase = devpriv->counters + ADDI_TCW_IRQ_REG;
46 outl(0x0, iobase + APCI1564_COUNTER(0));
47 outl(0x0, iobase + APCI1564_COUNTER(1));
48 outl(0x0, iobase + APCI1564_COUNTER(2));
51 /* disable Timer interrupt */
52 outl(0x0, devpriv->timer + ADDI_TCW_CTRL_REG);
55 /* Loading Timebase */
56 outl(data[2], devpriv->timer + ADDI_TCW_TIMEBASE_REG);
58 /* Loading the Reload value */
59 outl(data[3], devpriv->timer + ADDI_TCW_RELOAD_REG);
61 ctrl = inl(devpriv->timer + ADDI_TCW_CTRL_REG);
63 ctrl |= (2 << 13) | 0x10;
65 outl(ctrl, devpriv->timer + ADDI_TCW_CTRL_REG);
70 static int apci1564_timer_insn_write(struct comedi_device *dev,
71 struct comedi_subdevice *s,
72 struct comedi_insn *insn,
75 struct apci1564_private *devpriv = dev->private;
78 ctrl = inl(devpriv->timer + ADDI_TCW_CTRL_REG);
80 case 0: /* Stop The Timer */
83 case 1: /* Enable the Timer */
88 outl(ctrl, devpriv->timer + ADDI_TCW_CTRL_REG);
93 static int apci1564_timer_insn_read(struct comedi_device *dev,
94 struct comedi_subdevice *s,
95 struct comedi_insn *insn,
98 struct apci1564_private *devpriv = dev->private;
100 /* Stores the status of the Timer */
101 data[0] = inl(devpriv->timer + ADDI_TCW_STATUS_REG) & 0x1;
103 /* Stores the Actual value of the Timer */
104 data[1] = inl(devpriv->timer + ADDI_TCW_VAL_REG);
109 static int apci1564_counter_insn_config(struct comedi_device *dev,
110 struct comedi_subdevice *s,
111 struct comedi_insn *insn,
114 struct apci1564_private *devpriv = dev->private;
115 unsigned int chan = CR_CHAN(insn->chanspec);
116 unsigned long iobase = devpriv->counters + APCI1564_COUNTER(chan);
119 devpriv->tsk_current = current;
121 /* First Stop The Counter */
122 ctrl = inl(iobase + ADDI_TCW_CTRL_REG);
125 outl(ctrl, iobase + ADDI_TCW_CTRL_REG);
127 /* Set the reload value */
128 outl(data[3], iobase + ADDI_TCW_RELOAD_REG);
131 /* - Disable the hardware */
132 /* - Disable the counter mode */
133 /* - Disable the warning */
134 /* - Disable the reset */
135 /* - Disable the timer mode */
136 /* - Enable the counter mode */
139 ctrl |= 0x80000 | (data[4] << 16);
140 outl(ctrl, iobase + ADDI_TCW_CTRL_REG);
142 /* Enable or Disable Interrupt */
144 ctrl |= (data[1] << 1);
145 outl(ctrl, iobase + ADDI_TCW_CTRL_REG);
147 /* Set the Up/Down selection */
149 ctrl |= (data[6] << 18);
150 outl(ctrl, iobase + ADDI_TCW_CTRL_REG);
155 static int apci1564_counter_insn_write(struct comedi_device *dev,
156 struct comedi_subdevice *s,
157 struct comedi_insn *insn,
160 struct apci1564_private *devpriv = dev->private;
161 unsigned int chan = CR_CHAN(insn->chanspec);
162 unsigned long iobase = devpriv->counters + APCI1564_COUNTER(chan);
165 ctrl = inl(iobase + ADDI_TCW_CTRL_REG);
167 case 0: /* Stops the Counter subdevice */
170 case 1: /* Start the Counter subdevice */
174 case 2: /* Clears the Counter subdevice */
179 outl(ctrl, iobase + ADDI_TCW_CTRL_REG);
184 static int apci1564_counter_insn_read(struct comedi_device *dev,
185 struct comedi_subdevice *s,
186 struct comedi_insn *insn,
189 struct apci1564_private *devpriv = dev->private;
190 unsigned int chan = CR_CHAN(insn->chanspec);
191 unsigned long iobase = devpriv->counters + APCI1564_COUNTER(chan);
194 /* Read the Counter Actual Value. */
195 data[0] = inl(iobase + ADDI_TCW_VAL_REG);
197 status = inl(iobase + ADDI_TCW_STATUS_REG);
198 data[1] = (status >> 1) & 1; /* software trigger status */
199 data[2] = (status >> 2) & 1; /* hardware trigger status */
200 data[3] = (status >> 3) & 1; /* software clear status */
201 data[4] = (status >> 0) & 1; /* overflow status */