2 // Copyright (c) 2010-2017 Intel Corporation
4 // Licensed under the Apache License, Version 2.0 (the "License");
5 // you may not use this file except in compliance with the License.
6 // You may obtain a copy of the License at
8 // http://www.apache.org/licenses/LICENSE-2.0
10 // Unless required by applicable law or agreed to in writing, software
11 // distributed under the License is distributed on an "AS IS" BASIS,
12 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 // See the License for the specific language governing permissions and
14 // limitations under the License.
26 int msr_fd[RTE_MAX_LCORE];
36 for (uint32_t i = 0; i < sizeof(msr_fd)/sizeof(*msr_fd); ++i, n_msr_fd = i) {
37 snprintf(msr_path, sizeof(msr_path), "/dev/cpu/%u/msr", i);
38 msr_fd[i] = open(msr_path, O_RDWR);
40 return i == 0? -1 : 0;
47 void msr_cleanup(void)
49 for (int i = 0; i < n_msr_fd; ++i) {
56 int msr_read(uint64_t *ret, int lcore_id, off_t offset)
58 if (lcore_id > n_msr_fd) {
62 if (0 > pread(msr_fd[lcore_id], ret, sizeof(uint64_t), offset)) {
69 int msr_write(int lcore_id, uint64_t val, off_t offset)
71 if (lcore_id > n_msr_fd) {
75 if (sizeof(uint64_t) != pwrite(msr_fd[lcore_id], &val, sizeof(uint64_t), offset)) {
78 // plogx_dbg("\t\tmsr_write(core %d, offset %x, val %lx)\n", lcore_id, (int)offset, val);