2 // Copyright (c) 2010-2017 Intel Corporation
4 // Licensed under the Apache License, Version 2.0 (the "License");
5 // you may not use this file except in compliance with the License.
6 // You may obtain a copy of the License at
8 // http://www.apache.org/licenses/LICENSE-2.0
10 // Unless required by applicable law or agreed to in writing, software
11 // distributed under the License is distributed on an "AS IS" BASIS,
12 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 // See the License for the specific language governing permissions and
14 // limitations under the License.
19 #include <rte_sched.h>
20 #include <rte_version.h>
26 #include "prox_port_cfg.h"
30 #define TEN_GIGABIT 1250000000
31 #define QUEUE_SIZES 128
32 #define NB_PIPES 32768
34 #define RING_RX_SIZE 256
35 #define NB_RX_RING_DESC 256
36 #define NB_TX_RING_DESC 256
38 /* 1500000 milliseconds */
39 #define DEFAULT_CPE_TIMEOUT_MS 1500000
42 #if DEFAULT_CPE_TIMEOUT_MS < (DRAIN_TIMEOUT/3000000)
43 #error DEFAULT_CPE_TIMEOUT_MS too small (needs to be at least 2 ms)
46 static const struct rte_eth_conf default_port_conf = {
49 .header_split = 0, /* Header Split disabled */
50 .hw_ip_checksum = 0, /* IP checksum offload disabled */
51 .hw_vlan_filter = 0, /* VLAN filtering disabled */
52 .hw_vlan_strip = 0, /* VLAN filtering disabled */
53 .jumbo_frame = 0, /* Jumbo frame support disabled */
54 .hw_strip_crc = 1, /* CRC stripped by hardware --- always set to 1 in VF */
64 .lsc = 1, /* lsc interrupt feature enabled */
68 static const struct rte_eth_rxconf default_rx_conf = {
72 static struct rte_eth_txconf default_tx_conf = {
78 .tx_free_thresh = 32, /* Use PMD default values */
79 .tx_rs_thresh = 32, /* Use PMD default values */
82 static struct rte_sched_port_params port_params_default = {
85 .mtu = 6 + 6 + 4 + 4 + 2 + 1500,
87 .frame_overhead = RTE_SCHED_FRAME_OVERHEAD_DEFAULT,
88 .n_subports_per_port = 1,
89 .n_pipes_per_subport = NB_PIPES,
90 .qsize = {QUEUE_SIZES, QUEUE_SIZES, QUEUE_SIZES, QUEUE_SIZES},
91 .pipe_profiles = NULL,
92 .n_pipe_profiles = 1 /* only one profile */
95 static struct rte_sched_pipe_params pipe_params_default = {
96 .tb_rate = TEN_GIGABIT / NB_PIPES,
99 .tc_rate = {TEN_GIGABIT / NB_PIPES, TEN_GIGABIT / NB_PIPES, TEN_GIGABIT / NB_PIPES, TEN_GIGABIT / NB_PIPES},
102 .wrr_weights = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1},
105 static struct rte_sched_subport_params subport_params_default = {
106 .tb_rate = TEN_GIGABIT,
108 .tc_rate = {TEN_GIGABIT, TEN_GIGABIT, TEN_GIGABIT, TEN_GIGABIT},
109 .tc_period = 40, /* default was 10 */
112 void set_global_defaults(__attribute__((unused)) struct prox_cfg *prox_cfg)
116 void set_task_defaults(struct prox_cfg* prox_cfg, struct lcore_cfg* lcore_cfg_init)
118 prox_cfg->master = RTE_MAX_LCORE;
120 for (uint32_t i = 0; i < RTE_DIM(prox_cfg->cpe_table_ports); ++i) {
121 prox_cfg->cpe_table_ports[i] = -1;
124 for (uint8_t lcore_id = 0; lcore_id < RTE_MAX_LCORE; ++lcore_id) {
125 struct lcore_cfg *cur_lcore_cfg_init = &lcore_cfg_init[lcore_id];
126 cur_lcore_cfg_init->id = lcore_id;
127 for (uint8_t task_id = 0; task_id < MAX_TASKS_PER_CORE; ++task_id) {
128 struct task_args *targ = &cur_lcore_cfg_init->targs[task_id];
129 for (uint8_t port_id = 0; port_id < PROX_MAX_PORTS; ++port_id) {
130 targ->rx_port_queue[port_id].port = OUT_DISCARD;
132 targ->flags |= TASK_ARG_DROP;
133 targ->flags |= TASK_ARG_QINQ_ACL;
134 targ->cpe_table_timeout_ms = DEFAULT_CPE_TIMEOUT_MS;
135 targ->n_flows = NB_PIPES;
136 /* configure default values for QoS (can be overwritten by config) */
137 targ->qos_conf.port_params = port_params_default;
138 targ->qos_conf.pipe_params[0] = pipe_params_default;
139 targ->qos_conf.subport_params[0] = subport_params_default;
140 targ->qos_conf.port_params.pipe_profiles = targ->qos_conf.pipe_params;
141 targ->qos_conf.port_params.rate = TEN_GIGABIT;
142 targ->qinq_tag = ETYPE_8021ad;
143 targ->n_concur_conn = 8192*2;
145 for (uint8_t port_id = 0; port_id < PROX_MAX_PORTS; ++port_id) {
146 targ->tx_port_queue[port_id].port = OUT_DISCARD;
149 for (uint8_t i = 0; i < PROX_MAX_PORTS; ++i) {
150 targ->mapping[i] = i; // identity
153 targ->cbs = ETHER_MAX_LEN;
154 targ->ebs = ETHER_MAX_LEN;
155 targ->pbs = ETHER_MAX_LEN;
157 targ->n_max_rules = 1024;
158 targ->ring_size = RING_RX_SIZE;
159 targ->nb_cache_mbuf = MAX_PKT_BURST * 4;
160 targ->overhead = ETHER_CRC_LEN + 20;
162 targ->tunnel_hop_limit = 3;
163 targ->ctrl_freq = 1000;
164 targ->lb_friend_core = 0xFF;
165 targ->mbuf_size = MBUF_SIZE;
166 targ->n_pkts = 1024*64;
167 targ->runtime_flags |= TASK_TX_CRC;
168 targ->accuracy_limit_nsec = 5000;
173 void set_port_defaults(void)
175 for (uint8_t i = 0; i < PROX_MAX_PORTS; ++i ) {
176 prox_port_cfg[i].promiscuous = 1;
177 prox_port_cfg[i].n_rxd = NB_RX_RING_DESC;
178 prox_port_cfg[i].n_txd = NB_TX_RING_DESC;
179 prox_port_cfg[i].port_conf = default_port_conf;
180 prox_port_cfg[i].tx_conf = default_tx_conf;
181 prox_port_cfg[i].rx_conf = default_rx_conf;
182 prox_port_cfg[i].rx_ring[0] = '\0';
183 prox_port_cfg[i].tx_ring[0] = '\0';
184 prox_port_cfg[i].mtu = PROX_MTU;